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Mon, 26 Feb 2024 13:11:26 -0800 Received: from localhost.localdomain (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 26 Feb 2024 15:11:25 -0600 From: Harry Wentland To: , CC: , Alex Hung , Harry Wentland Subject: [RFC PATCH v4 32/42] drm/amd/display: Add support for sRGB Inverse EOTF in SHAPER block Date: Mon, 26 Feb 2024 16:10:46 -0500 Message-ID: <20240226211100.100108-33-harry.wentland@amd.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240226211100.100108-1-harry.wentland@amd.com> References: <20240226211100.100108-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A106:EE_|SA1PR12MB6798:EE_ X-MS-Office365-Filtering-Correlation-Id: 76afa40c-68cf-4ef3-7317-08dc370f7e91 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MDLelFUmrNRNjXnLD6oNUFRoBUly2A5/O9yN7ocVl9q6pFyyT/RMqQPvwi//NZCXrOODIq3UtCxu8tlBX7gJIPMp2MLo37sWKdUadBr0HzAX8sd3SzmpOXInnieOxCPE3+Mzo5yXStJv5bvzb99egXY1XwIJgu0lcZb4n/PuvUQm++zJonGvDAnvfZShlf9CI1aNYa59TsmbVXQzOTlhP04r03n6v6gnMskMyCTmXDxZQFI1VvvXPs2f7GKCXZHkfxkWDaaPgNlyLDFVs6Sr5dtT0FdEUiHjhLjIM1x+ikxKxR61nFkNEcD8YQK5bb3Pb9FBs/JHVnG0V1K+wiJF6d9qVLFoF3gd4YuXwZ93vPDOtUb91+Qh7pTNFgHrFCsCdrbXdHjFMchIbF/a3sQbPgdDR3j3yakhMMGeKOaclT2wVXaxBPWc2Z/yleu6wL5OMjd0SfYi6YV8N8MERlpKqPp/9Xv/2Ay+UkUblAar5dqwEW5/41tqJqHOm12Iy1cK0hoUyJxBrxe8//juzIERcg9B/czBBoesVaFoiir08jML/s1kWGCcSS/UrNF2DEICjF/FJ+fS1jU+UoQJmsPs1oIM/QoAPq45OJgdTjWMw68vtove5fb+VWucbusti7QBbivcG9lVLm1LQXQmeotFMNAN2ZlEV4SRkqI/NH6IJmT7wjcx1jAcZoiwcj1JI+zDW1bJUxltkjUqwAYIl2zFjRC7YKg//C0gFXPQ6DD5K+TljSfkCs3JvKWgdY2Itp2u X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 21:11:26.6797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76afa40c-68cf-4ef3-7317-08dc370f7e91 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A106.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6798 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Alex Hung Expose a 2nd curve colorop with support for DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF and program HW to perform the sRGB Inverse EOTF on the shaper block when the colorop is not in bypass. With this change the follow IGT tests pass: kms_colorop --run plane-XR30-XR30-srgb_inv_eotf kms_colorop --run plane-XR30-XR30-srgb_eotf-srgb_inv_eotf The color pipeline now consists of the following colorops: 1. 1D curve colorop w/ sRGB EOTF support 2. 1D curve colorop w/ sRGB Inverse EOTF support Signed-off-by: Alex Hung Signed-off-by: Harry Wentland Co-developed-by: Harry Wentland --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 76 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 20 ++++- .../amd/display/amdgpu_dm/amdgpu_dm_colorop.h | 1 + 3 files changed, 96 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 3ec759934669..8788cfd26abd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -1203,6 +1203,70 @@ __set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state, return __set_colorop_in_tf_1d_curve(dc_plane_state, colorop_state); } +static int +__set_colorop_in_shaper_1d_curve(struct dc_plane_state *dc_plane_state, + struct drm_colorop_state *colorop_state) +{ + struct dc_transfer_func *tf = dc_plane_state->in_shaper_func; + struct drm_colorop *colorop = colorop_state->colorop; + struct drm_device *drm = colorop->dev; + const struct drm_color_lut *shaper_lut; + uint32_t shaper_size; + + if (colorop->type != DRM_COLOROP_1D_CURVE && + colorop_state->curve_1d_type != DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) + return -EINVAL; + + if (colorop_state->bypass) { + tf->type = TF_TYPE_BYPASS; + tf->tf = TRANSFER_FUNCTION_LINEAR; + return 0; + } + + drm_dbg(drm, "Shaper colorop with ID: %d\n", colorop->base.id); + + if (colorop->type == DRM_COLOROP_1D_CURVE) { + tf->type = TF_TYPE_DISTRIBUTED_POINTS; + tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type); + tf->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE; + return __set_output_tf(tf, shaper_lut, shaper_size, false); + } + + return -EINVAL; +} + +static int +__set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state, + struct drm_colorop *colorop) +{ + struct drm_colorop *old_colorop; + struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; + struct drm_atomic_state *state = plane_state->state; + int i = 0; + + old_colorop = colorop; + + /* 2nd op: 1d curve - shaper */ + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { + if (new_colorop_state->colorop == old_colorop && + new_colorop_state->curve_1d_type == DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) { + colorop_state = new_colorop_state; + break; + } + + if (new_colorop_state->colorop == old_colorop) { + colorop_state = new_colorop_state; + break; + } + } + + if (!colorop_state) + return -EINVAL; + + return __set_colorop_in_shaper_1d_curve(dc_plane_state, colorop_state); +} + static int amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) @@ -1258,6 +1322,7 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) { struct drm_colorop *colorop = plane_state->color_pipeline; + struct drm_device *dev = plane_state->plane->dev; int ret; /* 1D Curve - DEGAM TF */ @@ -1269,6 +1334,17 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, if (ret) return ret; + /* 1D Curve - SHAPER TF */ + colorop = colorop->next; + if (!colorop) { + drm_dbg(dev, "no Shaper TF colorop found\n"); + return -EINVAL; + } + + ret = __set_dm_plane_colorop_shaper(plane_state, dc_plane_state, colorop); + if (ret) + return ret; + return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c index e8b7fc8bb0f1..0d1626abf577 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c @@ -34,9 +34,12 @@ const u64 amdgpu_dm_supported_degam_tfs = BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF); + const u64 amdgpu_dm_supported_shaper_tfs = + BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF); + int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list) { - struct drm_colorop *op; + struct drm_colorop *op, *prev_op; struct drm_device *dev = plane->dev; int ret; @@ -54,5 +57,20 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr list->type = op->base.id; list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", op->base.id); + prev_op = op; + + /* 1D curve - SHAPER TF */ + op = kzalloc(sizeof(struct drm_colorop), GFP_KERNEL); + if (!op) { + DRM_ERROR("KMS: Failed to allocate colorop\n"); + return -ENOMEM; + } + + ret = drm_colorop_curve_1d_init(dev, op, plane, amdgpu_dm_supported_shaper_tfs); + if (ret) + return ret; + + drm_colorop_set_next_property(prev_op, op); + return 0; } \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h index f16de6a9fbde..c4b1b187e9bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h @@ -28,6 +28,7 @@ #define __AMDGPU_DM_COLOROP_H__ extern const u64 amdgpu_dm_supported_degam_tfs; +extern const u64 amdgpu_dm_supported_shaper_tfs; int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list);