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Fri, 29 Mar 2024 20:52:33 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 30 Mar 2024 05:52:29 +0200 Subject: [PATCH] drm/msm/dpu: fix vblank IRQ handling for command panels MIME-Version: 1.0 Message-Id: <20240330-dpu-fix-irqs-v1-1-39b8d4e4e918@linaro.org> X-B4-Tracking: v=1; b=H4sIAH2MB2YC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxMDY2MD3ZSCUt20zArdzKLCYl1Ts9QkA4u05CTLFBMloJaColSgHNi46Nj aWgCpieQ0XgAAAA== To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3329; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Cd4wDXm0dJqTu9lVUdgD8jllEmwa9/NyuEoxlOOn5KM=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQxp7T2O55IWA6hiBHWdaV1ewH7jlXLYji7NN8n1tiM26+ 3dWLrvSyWjMwsDIxSArpsjiU9AyNWZTctiHHVPrYQaxMoFMYeDiFICJpHJxMCyvaTRqveOXeHmT nON647ApagwG+zQNPZQfpGZu1LZh2qXA4rJS8HiBE3/ohfbJItlR3oFGH3MmfEqdbSD/8vji7/t Tt5YIPKxXmK/5sG//khL7ZpMGP/WFnrNVdpcq6usq7PcvlLu12/iOwuHam//UfOuiWR2y0l2c67 +tYkrkP92258GZSwE8otP14oVkjilomO6W3Fkbv6jpu9rbZNkLemKKU7POLGXpq2zSv7jq/7dTB nNefBFp67i9+VusTNcW9V73CSc/fNruZttaeWOrvvRrVzf5l0rXT9otO6n+ol/0082qJQcerZms 3i2btOJV48kF7Js/yKgnzuCY6SAT5tvf7nT1Vcqa7fMqAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In case of CMD DSI panels, the vblank IRQ can be used outside of irq_enable/irq_disable pair. This results in the following kind of messages. Move assignment of IRQ indices to atomic_enable / atomic_disable callbacks. [dpu error]invalid IRQ=[134217727, 31] [drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err id:31 pp:0 ret:-22, enable true/0 [drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err id:31 pp:0 ret:-22, enable false/0 Fixes: d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set") Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) --- base-commit: 13ee4a7161b6fd938aef6688ff43b163f6d83e37 change-id: 20240330-dpu-fix-irqs-56eb08fcb9d4 Best regards, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index fc1d5736d7fc..2a2b607bd1ab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -280,14 +280,6 @@ static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->idx - PINGPONG_0, phys_enc->vblank_refcount); - phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; - phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; - - if (phys_enc->has_intf_te) - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; - else - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; - dpu_core_irq_register_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG], dpu_encoder_phys_cmd_pp_tx_done_irq, @@ -318,10 +310,6 @@ static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc) dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]); dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]); - - phys_enc->irq[INTR_IDX_CTL_START] = 0; - phys_enc->irq[INTR_IDX_PINGPONG] = 0; - phys_enc->irq[INTR_IDX_RDPTR] = 0; } static void dpu_encoder_phys_cmd_tearcheck_config( @@ -472,6 +460,14 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) return; } + phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; + phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; + + if (phys_enc->has_intf_te) + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; + else + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; + dpu_encoder_phys_cmd_enable_helper(phys_enc); phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -563,6 +559,10 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); } + phys_enc->irq[INTR_IDX_CTL_START] = 0; + phys_enc->irq[INTR_IDX_PINGPONG] = 0; + phys_enc->irq[INTR_IDX_RDPTR] = 0; + phys_enc->enable_state = DPU_ENC_DISABLED; }