diff mbox series

[CI,1/2] Revert "drm/i915/gt: Do not generate the command streamer for all the CCS"

Message ID 20240422162731.7046-2-andi.shyti@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Force CCS mode to the maximum | expand

Commit Message

Andi Shyti April 22, 2024, 4:27 p.m. UTC 
This reverts commit ea315f98e5d6d3191b74beb0c3e5fc16081d517c.
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 -----------------
 1 file changed, 17 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8c44af1c3451..476651bd0a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -874,23 +874,6 @@  static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 		info->engine_mask &= ~BIT(GSC0);
 	}
 
-	/*
-	 * Do not create the command streamer for CCS slices beyond the first.
-	 * All the workload submitted to the first engine will be shared among
-	 * all the slices.
-	 *
-	 * Once the user will be allowed to customize the CCS mode, then this
-	 * check needs to be removed.
-	 */
-	if (IS_DG2(gt->i915)) {
-		u8 first_ccs = __ffs(CCS_MASK(gt));
-
-		/* Mask off all the CCS engine */
-		info->engine_mask &= ~GENMASK(CCS3, CCS0);
-		/* Put back in the first CCS engine */
-		info->engine_mask |= BIT(_CCS(first_ccs));
-	}
-
 	return info->engine_mask;
 }