diff mbox series

[CI,2/2] drm/i915/gt: Force ccs_mode 4

Message ID 20240422162731.7046-3-andi.shyti@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Force CCS mode to the maximum | expand

Commit Message

Andi Shyti April 22, 2024, 4:27 p.m. UTC 
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 044219c5960a..d0f181a8e73e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
@@ -10,29 +10,33 @@ 
 
 void intel_gt_apply_ccs_mode(struct intel_gt *gt)
 {
+	unsigned long ccs_mask = CCS_MASK(gt);
 	int cslice;
 	u32 mode = 0;
-	int first_ccs = __ffs(CCS_MASK(gt));
+	int first_ccs = __ffs(ccs_mask);
 
 	if (!IS_DG2(gt->i915))
 		return;
 
 	/* Build the value for the fixed CCS load balancing */
 	for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
-		if (CCS_MASK(gt) & BIT(cslice))
+		if (CCS_MASK(gt) & BIT(cslice)) {
 			/*
 			 * If available, assign the cslice
 			 * to the first available engine...
 			 */
 			mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
-
-		else
+			first_ccs = find_next_bit(&ccs_mask,
+						  I915_MAX_CCS,
+						  first_ccs + 1);
+		} else {
 			/*
 			 * ... otherwise, mark the cslice as
 			 * unavailable if no CCS dispatches here
 			 */
 			mode |= XEHP_CCS_MODE_CSLICE(cslice,
 						     XEHP_CCS_MODE_CSLICE_MASK);
+		}
 	}
 
 	intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);