| Message ID | 20240423082722.843587-2-kuro.chung@ite.com.tw (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/bridge: it6505: fix hibernate to resume no display issue | expand |
On Tue, Apr 23, 2024 at 10:16 AM kuro <kuro.chung@ite.com.tw> wrote: > > From: Kuro <kuro.chung@ite.com.tw> > > ITE added a FIFO reset bit for input video. When system power resume, > the TTL input of it6505 may get some noise before video signal stable > and the hardware function reset is required. > But the input FIFO reset will also trigger error interrupts of output module rising. > Thus, it6505 have to wait a period can clear those expected error interrupts > caused by manual hardware reset in one interrupt handler calling to avoid interrupt looping. > > Signed-off-by: Kuro Chung <kuro.chung@ite.corp-partner.google.com> > > --- > drivers/gpu/drm/bridge/ite-it6505.c | 73 +++++++++++++++++++---------- > 1 file changed, 49 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c > index b53da9bb65a16..ae7f4c7ec6dd0 100644 > --- a/drivers/gpu/drm/bridge/ite-it6505.c > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > @@ -1317,9 +1317,15 @@ static void it6505_video_reset(struct it6505 *it6505) > it6505_link_reset_step_train(it6505); > it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE); > it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00); > - it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); > + > + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x02); > + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00); > + > it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO); > it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00); > + > + it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); > + usleep_range(1000, 2000); > it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00); Can any of these magic values be defined as macros? > } > > @@ -2249,12 +2255,11 @@ static void it6505_link_training_work(struct work_struct *work) > if (ret) { > it6505->auto_train_retry = AUTO_TRAIN_RETRY; > it6505_link_train_ok(it6505); > - return; > } else { > it6505->auto_train_retry--; > + it6505_dump(it6505); > } > > - it6505_dump(it6505); > } > > static void it6505_plugged_status_to_codec(struct it6505 *it6505) > @@ -2475,31 +2480,53 @@ static void it6505_irq_link_train_fail(struct it6505 *it6505) > schedule_work(&it6505->link_works); > } > > -static void it6505_irq_video_fifo_error(struct it6505 *it6505) > +static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) > { > - struct device *dev = &it6505->client->dev; > - > - DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt"); > - it6505->auto_train_retry = AUTO_TRAIN_RETRY; > - flush_work(&it6505->link_works); > - it6505_stop_hdcp(it6505); > - it6505_video_reset(it6505); > + return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); > } > > -static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) > +static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status) > { > struct device *dev = &it6505->client->dev; > + int reg_0d, reg_int03; > > - DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt"); > - it6505->auto_train_retry = AUTO_TRAIN_RETRY; > - flush_work(&it6505->link_works); > - it6505_stop_hdcp(it6505); > - it6505_video_reset(it6505); > -} > + /* > + * When video SCDT change with video not stable, > + * Or video FIFO error, need video reset > + */ > > -static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) > -{ > - return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); > + if ((!it6505_get_video_status(it6505) && > + (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_status))) || > + (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW, (unsigned int *) int_status)) || > + (it6505_test_bit(BIT_INT_VID_FIFO_ERROR, (unsigned int *) int_status))) { > + > + it6505->auto_train_retry = AUTO_TRAIN_RETRY; > + flush_work(&it6505->link_works); > + it6505_stop_hdcp(it6505); > + it6505_video_reset(it6505); > + > + usleep_range(10000, 11000); > + > + /* > + * Clear FIFO error IRQ to prevent fifo error -> reset loop > + * HW will trigger SCDT change IRQ again when video stable > + */ > + > + reg_int03 = it6505_read(it6505, INT_STATUS_03); > + reg_0d = it6505_read(it6505, REG_SYSTEM_STS); > + > + reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW)); > + it6505_write(it6505, INT_STATUS_03, reg_int03); > + > + DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03); Is this correct? Doesreg_int03 contain reg08? > + DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d); > + > + return; > + } > + > + > + if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_status)) > + it6505_irq_scdt(it6505); > } > > static irqreturn_t it6505_int_threaded_handler(int unused, void *data) > @@ -2512,15 +2539,12 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) > } irq_vec[] = { > { BIT_INT_HPD, it6505_irq_hpd }, > { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq }, > - { BIT_INT_SCDT, it6505_irq_scdt }, > { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail }, > { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done }, > { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail }, > { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check }, > { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error }, > { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail }, > - { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error }, > - { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow }, > }; > int int_status[3], i; > > @@ -2550,6 +2574,7 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) > if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status)) > irq_vec[i].handler(it6505); > } > + it6505_irq_video_handler(it6505, (unsigned int *) int_status); > } > > pm_runtime_put_sync(dev); > -- > 2.25.1 >
-----Original Message----- From: Robert Foss <rfoss@kernel.org> Sent: Tuesday, April 23, 2024 9:50 PM To: Kuro Chung (鐘仕廷) <kuro.chung@ite.com.tw> Cc: Allen Chen <allen.chen@ite.com.tw>; Pin-yen Lin <treapking@chromium.org>; Kenneth Hung (洪家倫) <Kenneth.Hung@ite.com.tw>; Kuro Chung <kuro.chung@ite.corp-partner.google.com>; Andrzej Hajda <andrzej.hajda@intel.com>; Neil Armstrong <neil.armstrong@linaro.org>; Laurent Pinchart <Laurent.pinchart@ideasonboard.com>; Jonas Karlman <jonas@kwiboo.se>; Jernej Skrabec <jernej.skrabec@gmail.com>; Maarten Lankhorst <maarten.lankhorst@linux.intel.com>; Maxime Ripard <mripard@kernel.org>; Thomas Zimmermann <tzimmermann@suse.de>; David Airlie <airlied@gmail.com>; Daniel Vetter <daniel@ffwll.ch>; open list:DRM DRIVERS <dri-devel@lists.freedesktop.org>; open list <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v6 1/1] drm/bridge: it6505: fix hibernate to resume no display issue On Tue, Apr 23, 2024 at 10:16 AM kuro <kuro.chung@ite.com.tw> wrote: > > From: Kuro <kuro.chung@ite.com.tw> > > ITE added a FIFO reset bit for input video. When system power resume, > the TTL input of it6505 may get some noise before video signal stable > and the hardware function reset is required. > But the input FIFO reset will also trigger error interrupts of output module rising. > Thus, it6505 have to wait a period can clear those expected error > interrupts caused by manual hardware reset in one interrupt handler calling to avoid interrupt looping. > > Signed-off-by: Kuro Chung <kuro.chung@ite.corp-partner.google.com> > > --- > drivers/gpu/drm/bridge/ite-it6505.c | 73 > +++++++++++++++++++---------- > 1 file changed, 49 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c > b/drivers/gpu/drm/bridge/ite-it6505.c > index b53da9bb65a16..ae7f4c7ec6dd0 100644 > --- a/drivers/gpu/drm/bridge/ite-it6505.c > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > @@ -1317,9 +1317,15 @@ static void it6505_video_reset(struct it6505 *it6505) > it6505_link_reset_step_train(it6505); > it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE); > it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00); > - it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); > + > + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x02); > + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, > + 0x00); > + > it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO); > it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, > 0x00); > + > + it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); > + usleep_range(1000, 2000); > it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00); Can any of these magic values be defined as macros? -> I will modify the code 0x02 to TX_FIFO_RESET > } > > @@ -2249,12 +2255,11 @@ static void it6505_link_training_work(struct work_struct *work) > if (ret) { > it6505->auto_train_retry = AUTO_TRAIN_RETRY; > it6505_link_train_ok(it6505); > - return; > } else { > it6505->auto_train_retry--; > + it6505_dump(it6505); > } > > - it6505_dump(it6505); > } > > static void it6505_plugged_status_to_codec(struct it6505 *it6505) @@ > -2475,31 +2480,53 @@ static void it6505_irq_link_train_fail(struct it6505 *it6505) > schedule_work(&it6505->link_works); > } > > -static void it6505_irq_video_fifo_error(struct it6505 *it6505) > +static bool it6505_test_bit(unsigned int bit, const unsigned int > +*addr) > { > - struct device *dev = &it6505->client->dev; > - > - DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt"); > - it6505->auto_train_retry = AUTO_TRAIN_RETRY; > - flush_work(&it6505->link_works); > - it6505_stop_hdcp(it6505); > - it6505_video_reset(it6505); > + return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % > + BITS_PER_BYTE)); > } > > -static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) > +static void it6505_irq_video_handler(struct it6505 *it6505, const int > +*int_status) > { > struct device *dev = &it6505->client->dev; > + int reg_0d, reg_int03; > > - DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt"); > - it6505->auto_train_retry = AUTO_TRAIN_RETRY; > - flush_work(&it6505->link_works); > - it6505_stop_hdcp(it6505); > - it6505_video_reset(it6505); > -} > + /* > + * When video SCDT change with video not stable, > + * Or video FIFO error, need video reset > + */ > > -static bool it6505_test_bit(unsigned int bit, const unsigned int > *addr) -{ > - return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); > + if ((!it6505_get_video_status(it6505) && > + (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_status))) || > + (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW, (unsigned int *) int_status)) || > + (it6505_test_bit(BIT_INT_VID_FIFO_ERROR, (unsigned int > + *) int_status))) { > + > + it6505->auto_train_retry = AUTO_TRAIN_RETRY; > + flush_work(&it6505->link_works); > + it6505_stop_hdcp(it6505); > + it6505_video_reset(it6505); > + > + usleep_range(10000, 11000); > + > + /* > + * Clear FIFO error IRQ to prevent fifo error -> reset loop > + * HW will trigger SCDT change IRQ again when video stable > + */ > + > + reg_int03 = it6505_read(it6505, INT_STATUS_03); > + reg_0d = it6505_read(it6505, REG_SYSTEM_STS); > + > + reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW)); > + it6505_write(it6505, INT_STATUS_03, reg_int03); > + > + DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", > + reg_int03); Is this correct? Doesreg_int03 contain reg08? -> #define INT_STATUS_03 0x08 -> yes, INT03 is reg08 (offset), reg08 is more readable. > + DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d); > + > + return; > + } > + > + > + if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_status)) > + it6505_irq_scdt(it6505); > } > > static irqreturn_t it6505_int_threaded_handler(int unused, void > *data) @@ -2512,15 +2539,12 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) > } irq_vec[] = { > { BIT_INT_HPD, it6505_irq_hpd }, > { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq }, > - { BIT_INT_SCDT, it6505_irq_scdt }, > { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail }, > { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done }, > { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail }, > { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check }, > { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error }, > { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail }, > - { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error }, > - { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow }, > }; > int int_status[3], i; > > @@ -2550,6 +2574,7 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) > if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status)) > irq_vec[i].handler(it6505); > } > + it6505_irq_video_handler(it6505, (unsigned int *) > + int_status); > } > > pm_runtime_put_sync(dev); > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index b53da9bb65a16..ae7f4c7ec6dd0 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -1317,9 +1317,15 @@ static void it6505_video_reset(struct it6505 *it6505) it6505_link_reset_step_train(it6505); it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE); it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00); - it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); + + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x02); + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00); + it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO); it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00); + + it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); + usleep_range(1000, 2000); it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00); } @@ -2249,12 +2255,11 @@ static void it6505_link_training_work(struct work_struct *work) if (ret) { it6505->auto_train_retry = AUTO_TRAIN_RETRY; it6505_link_train_ok(it6505); - return; } else { it6505->auto_train_retry--; + it6505_dump(it6505); } - it6505_dump(it6505); } static void it6505_plugged_status_to_codec(struct it6505 *it6505) @@ -2475,31 +2480,53 @@ static void it6505_irq_link_train_fail(struct it6505 *it6505) schedule_work(&it6505->link_works); } -static void it6505_irq_video_fifo_error(struct it6505 *it6505) +static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) { - struct device *dev = &it6505->client->dev; - - DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt"); - it6505->auto_train_retry = AUTO_TRAIN_RETRY; - flush_work(&it6505->link_works); - it6505_stop_hdcp(it6505); - it6505_video_reset(it6505); + return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); } -static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) +static void it6505_irq_video_handler(struct it6505 *it6505, const int *int_status) { struct device *dev = &it6505->client->dev; + int reg_0d, reg_int03; - DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt"); - it6505->auto_train_retry = AUTO_TRAIN_RETRY; - flush_work(&it6505->link_works); - it6505_stop_hdcp(it6505); - it6505_video_reset(it6505); -} + /* + * When video SCDT change with video not stable, + * Or video FIFO error, need video reset + */ -static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) -{ - return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); + if ((!it6505_get_video_status(it6505) && + (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_status))) || + (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW, (unsigned int *) int_status)) || + (it6505_test_bit(BIT_INT_VID_FIFO_ERROR, (unsigned int *) int_status))) { + + it6505->auto_train_retry = AUTO_TRAIN_RETRY; + flush_work(&it6505->link_works); + it6505_stop_hdcp(it6505); + it6505_video_reset(it6505); + + usleep_range(10000, 11000); + + /* + * Clear FIFO error IRQ to prevent fifo error -> reset loop + * HW will trigger SCDT change IRQ again when video stable + */ + + reg_int03 = it6505_read(it6505, INT_STATUS_03); + reg_0d = it6505_read(it6505, REG_SYSTEM_STS); + + reg_int03 &= (BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW)); + it6505_write(it6505, INT_STATUS_03, reg_int03); + + DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", reg_int03); + DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d); + + return; + } + + + if (it6505_test_bit(INT_SCDT_CHANGE, (unsigned int *) int_status)) + it6505_irq_scdt(it6505); } static irqreturn_t it6505_int_threaded_handler(int unused, void *data) @@ -2512,15 +2539,12 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) } irq_vec[] = { { BIT_INT_HPD, it6505_irq_hpd }, { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq }, - { BIT_INT_SCDT, it6505_irq_scdt }, { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail }, { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done }, { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail }, { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check }, { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error }, { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail }, - { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error }, - { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow }, }; int int_status[3], i; @@ -2550,6 +2574,7 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status)) irq_vec[i].handler(it6505); } + it6505_irq_video_handler(it6505, (unsigned int *) int_status); } pm_runtime_put_sync(dev);