From patchwork Sun May 12 15:25:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Noralf_Tr=C3=B8nnes_via_B4_Relay?= X-Patchwork-Id: 13662746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D341C25B4F for ; Sun, 12 May 2024 15:25:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBC7810E135; Sun, 12 May 2024 15:25:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="cdV9NhZ/"; dkim-atps=neutral Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2A8B310E091 for ; Sun, 12 May 2024 15:25:48 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 5ED6560B55; Sun, 12 May 2024 15:25:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 0B327C32783; Sun, 12 May 2024 15:25:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715527547; bh=ts+cCu/hWWBZ2/giL/uZzZqvRs0AxvKShu5+0K6U5sI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cdV9NhZ/ININg6CF9a79xXpLMtw7RIpLYMI0ecqRoVd0fK3okvWoSJ4D6r6aJ4UWf K8rLSVNbqvLBdu15LwUKCDkfYe6khEC4CWooZUIDQaMxDH/JzwfmuCzvimxlTA758C 7nnsLl4+6mY4g7BHh/h1xk1X0pJI5Ux/oYDCdLORO5iswDkCMsEBgSUaIR5SWBz17h bhVDbBb0KCFWzSzCXmYXlIcFZcSvB/J5Pa5SVxFYcerH3ciAUs5qNZVt7ovszQXowe DU9j9lxaO0k1wqLxxAQTtsfhCepuPGjd+EgfXVJCqt3fEdbE8glDjfYvSkzsnBQr0B mt3g9w10ePA+w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 000A3C25B4F; Sun, 12 May 2024 15:25:46 +0000 (UTC) From: =?utf-8?q?Noralf_Tr=C3=B8nnes_via_B4_Relay?= Date: Sun, 12 May 2024 17:25:38 +0200 Subject: [PATCH v2 1/5] dt-bindings: display: panel: mipi-dbi-spi: Add a pixel format property MIME-Version: 1.0 Message-Id: <20240512-panel-mipi-dbi-rgb666-v2-1-49dd266328a0@tronnes.org> References: <20240512-panel-mipi-dbi-rgb666-v2-0-49dd266328a0@tronnes.org> In-Reply-To: <20240512-panel-mipi-dbi-rgb666-v2-0-49dd266328a0@tronnes.org> To: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kamlesh Gurudasani , Tommaso Merciai , =?utf-8?q?Noralf_T?= =?utf-8?q?r=C3=B8nnes?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1715527545; l=4015; i=noralf@tronnes.org; s=20221122; h=from:subject:message-id; bh=9ITKfCFJwTOhoO1zLTnicjr079G4OkFOQSpSOLXhMzc=; b=TkT6dLrKNLfT+J4qdjhC6Uew5jCI00Ml1tbaJFsNCfpHInZ+EKC/rHnKTOUurIelXTz3ApZmh EiRtCgHGk9mBtoHo57ZN1vcQQX+0vrMqld5twJyi3qi97n63P32zMnd X-Developer-Key: i=noralf@tronnes.org; a=ed25519; pk=0o9is4iddvvlrY3yON5SVtAbgPnVs0LfQsjfqR2Hvz8= X-Endpoint-Received: by B4 Relay for noralf@tronnes.org/20221122 with auth_id=8 X-Original-From: =?utf-8?q?Noralf_Tr=C3=B8nnes?= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: noralf@tronnes.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Noralf Trønnes The MIPI DBI 2.0 specification (2005) lists only two pixel formats for the Type C Interface (SPI) and that is 3-bits/pixel RGB111 with 2 options for bit layout. For Type A and B (parallel) the following formats are listed: RGB332, RGB444, RGB565, RGB666 and RGB888 (some have 2 options for the bit layout). Many MIPI DBI compatible controllers support all interface types on the same chip and often the manufacturers have chosen to provide support for the Type A/B interface pixel formats also on the Type C interface. Some chips provide many pixel formats with optional bit layouts over SPI, but the most common by far are RGB565 and RGB666. So even if the specification doesn't list these formats for the Type C interface, the industry has chosen to include them. The MIPI DCS specification lists the standard commands that can be sent over the MIPI DBI interface. The set_address_mode (36h) command has one bit in the parameter that controls RGB/BGR order: This bit controls the RGB data latching order transferred from the peripheral’s frame memory to the display device. This means that each supported RGB format also has a BGR variant. Based on this rationale document the following pixel formats describing the bit layout going over the wire: - RGB111 (option 1): x2r1g1b1r1g1b1 (2 pixels per byte) - BGR111 (option 1): x2b1g1r1b1g1r1 (2 pixels per byte) - RGB111 (option 2): x1r1g1b1x1r1g1b1 (2 pixels per byte) - BGR111 (option 2): x1b1g1r1x1b1g1r1 (2 pixels per byte) - RGB565: r5g6b5 (2 bytes) - BGR565: b5g6r5 (2 bytes) - RGB666: r6x2g6x2b6x2 (3 bytes) - BGR666: b6x2g6x2r6x2 (3 bytes) (x: don't care) v2: - Use 'default: r5g6b5' (Rob) Signed-off-by: Noralf Trønnes Reviewed-by: Rob Herring (Arm) --- .../bindings/display/panel/panel-mipi-dbi-spi.yaml | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml index e808215cb39e..8994549b4bff 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml @@ -50,6 +50,12 @@ description: | | Command or data | || + The standard defines one pixel format for type C: RGB111. The industry + however has decided to provide the type A/B interface pixel formats also on + the Type C interface and most common among these are RGB565 and RGB666. + The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR + order. This gives each supported RGB format a BGR variant. + The panel resolution is specified using the panel-timing node properties hactive (width) and vactive (height). The other mandatory panel-timing properties should be set to zero except clock-frequency which can be @@ -90,6 +96,28 @@ properties: spi-3wire: true + format: + description: > + Pixel format in bit order as going on the wire: + * `x2r1g1b1r1g1b1` - RGB111, 2 pixels per byte + * `x2b1g1r1b1g1r1` - BGR111, 2 pixels per byte + * `x1r1g1b1x1r1g1b1` - RGB111, 2 pixels per byte + * `x1b1g1r1x1b1g1r1` - BGR111, 2 pixels per byte + * `r5g6b5` - RGB565, 2 bytes + * `b5g6r5` - BGR565, 2 bytes + * `r6x2g6x2b6x2` - RGB666, 3 bytes + * `b6x2g6x2r6x2` - BGR666, 3 bytes + enum: + - x2r1g1b1r1g1b1 + - x2b1g1r1b1g1r1 + - x1r1g1b1x1r1g1b1 + - x1b1g1r1x1b1g1r1 + - r5g6b5 + - b5g6r5 + - r6x2g6x2b6x2 + - b6x2g6x2r6x2 + default: r5g6b5 + required: - compatible - reg @@ -116,6 +144,8 @@ examples: reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; write-only; + format = "r5g6b5"; + backlight = <&backlight>; width-mm = <35>;