From patchwork Thu May 16 08:53:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13665890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61EB9C25B74 for ; Thu, 16 May 2024 08:54:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 88DF310EC2F; Thu, 16 May 2024 08:54:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="oCya7zws"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA2CA10EAB1 for ; Thu, 16 May 2024 08:54:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715849658; x=1747385658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+szKxTSOgEIDRM/429ev80DKLMC3HChQWpJUPkuTqXg=; b=oCya7zwsPjLN0THZP2PJ3Ju80UUkTrIo/7hSJu+SlhbaVc2gSRC8M6f0 4WUH+QIRATL1RYz/fnKoQUUnlw2po6qdzb+9PLOd5ZdeF6TcQdEQO60QD Hql82XCQ+k54423ltKHSNUaelp/BYqbs5sPL+hXr4XD3gm1UxT6oL7IF/ 145q4NmgWvAsGtL2FEKOsECEtF+zCPSypKh9QZLoGN/f4XeSqirj0C7oE sjRQaGUm7CAEBhQk/vBjE9ag4dBIHqExfN+FIZIWbddK/vzV+yobs8qqN /IvzO5ChwTOHFOj6EOSoht6lUcck9zbAjxtwv1TD7fdObQM985woZXfTV w==; X-CSE-ConnectionGUID: nLbsUVKNTDCkpkBH0VjqyA== X-CSE-MsgGUID: eb4+NNYvSDuS2zsUYkeveQ== X-IronPort-AV: E=McAfee;i="6600,9927,11074"; a="11794408" X-IronPort-AV: E=Sophos;i="6.08,164,1712646000"; d="scan'208";a="11794408" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 01:54:18 -0700 X-CSE-ConnectionGUID: tDX0Yb4ARk2JfeStf81whQ== X-CSE-MsgGUID: LjED84FqT6KRSYPaOAMKpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,164,1712646000"; d="scan'208";a="36233540" Received: from tlonnber-mobl3.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.251.211.12]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 01:54:16 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: dri-devel@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 08/17] drm/display: Add missing aux less alpm wake related bits Date: Thu, 16 May 2024 11:53:42 +0300 Message-Id: <20240516085342.1559562-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240516085342.1559562-1-jouni.hogander@intel.com> References: <20240516085342.1559562-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 79bde372b152..f3ce8c483659 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -232,6 +232,8 @@ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) @@ -685,6 +687,7 @@ #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE (1 << 0) # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)