| Message ID | 20240527-msm-drm-dsc-dsi-video-upstream-4-v5-3-f797ffba4682@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC support to DSI video panel | expand |
On Mon, May 27, 2024 at 10:21:49PM +0800, Jun Nie wrote: > Enable compression bit in cfg2 register for DSC in the DSI case > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 5/27/2024 7:21 AM, Jun Nie wrote: > Enable compression bit in cfg2 register for DSC in the DSI case > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index f97221423249..34bfcfba3df2 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -177,6 +177,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > if (p->wide_bus_en && !dp_intf) > data_width = p->width >> 1; > > + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ > + if (p->compression_en && !dp_intf) > + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; Hi Jun, The DSC/DCE enablement registers were only moved to INTF in DPU 7.x and later. We should probably add some MDSS version check similar to what command mode INTF does here [1] Thanks, Jessica Zhang > + > hsync_data_start_x = hsync_start_x; > hsync_data_end_x = hsync_start_x + data_width - 1; > > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index f97221423249..34bfcfba3df2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -177,6 +177,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, if (p->wide_bus_en && !dp_intf) data_width = p->width >> 1; + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ + if (p->compression_en && !dp_intf) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1;
Enable compression bit in cfg2 register for DSC in the DSI case Signed-off-by: Jun Nie <jun.nie@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 ++++ 1 file changed, 4 insertions(+)