From patchwork Mon May 27 15:02:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ofir Bitton X-Patchwork-Id: 13675494 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66764C25B74 for ; Mon, 27 May 2024 15:03:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9949110E4E4; Mon, 27 May 2024 15:03:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=habana.ai header.i=@habana.ai header.b="cURU/Aju"; dkim-atps=neutral Received: from mail02.habana.ai (habanamailrelay02.habana.ai [62.90.112.121]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2633910E8D8 for ; Mon, 27 May 2024 15:02:36 +0000 (UTC) Received: internal info suppressed DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=habana.ai; s=default; t=1716822151; bh=mO1wTBrjD0PxLOyQ4AqovbqlEFzmz5ozW7rB391zFZg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cURU/AjuxgUwR+8nWz1e4LtyXs/e1DBcpK1wFmxlXep0ObfgsF5ZvgtPS+d1JnRxA IDCRW/4Q3AqLNCwF8+pE/UIHPPfOy17xNm2u4UmbHubR8HHKn/mLwi24TOgL9ARuY3 SgAxj0YCbgtYPDjAPpVD0+tRVCv5Mwlr//PIZFxz92HZhXJ/E9QzANce44CgngQVa6 n3GgTwg7LvtvysfhUUHW4uv3O/Ke6DreKA38CmDl//SOQWDafxsMm7tE8Dk+I9kQwK a95TKV6v7BESJqVpzvIKI0wBbPga4hVmshbGBnMIQd/H+b+2L1NRqxgzYdbNlfLXb+ SV8Zm+6KAnVaw== Received: from obitton-vm-u22.habana-labs.com (localhost [127.0.0.1]) by obitton-vm-u22.habana-labs.com (8.15.2/8.15.2/Debian-22ubuntu3) with ESMTP id 44RF2PiZ1954007; Mon, 27 May 2024 18:02:26 +0300 From: Ofir Bitton To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Tal Cohen Subject: [PATCH 8/8] accel/habanalabs: disable EQ interrupt after disabling pci Date: Mon, 27 May 2024 18:02:24 +0300 Message-Id: <20240527150224.1953969-8-obitton@habana.ai> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527150224.1953969-1-obitton@habana.ai> References: <20240527150224.1953969-1-obitton@habana.ai> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tal Cohen When sending disable pci msg towards firmware, there is a possibility that an EQ packet is already pending, disabling EQ interrupt will prevent this from happening. The interrupt will be re-enabled after reset. Signed-off-by: Tal Cohen Reviewed-by: Ofir Bitton --- drivers/accel/habanalabs/common/device.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c index 5ca7014def00..78e65c6b76a7 100644 --- a/drivers/accel/habanalabs/common/device.c +++ b/drivers/accel/habanalabs/common/device.c @@ -1502,10 +1502,11 @@ static void send_disable_pci_access(struct hl_device *hdev, u32 flags) if (hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0)) return; - /* verify that last EQs are handled before disabled is set */ + /* disable_irq also generates sync irq, this verifies that last EQs are handled + * before disabled is set. The IRQ will be enabled again in request_irq call. + */ if (hdev->cpu_queues_enable) - synchronize_irq(pci_irq_vector(hdev->pdev, - hdev->asic_prop.eq_interrupt_id)); + disable_irq(pci_irq_vector(hdev->pdev, hdev->asic_prop.eq_interrupt_id)); } }