From patchwork Wed May 29 20:07:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13679474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1180C25B75 for ; Wed, 29 May 2024 20:24:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B087112237; Wed, 29 May 2024 20:24:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XB9kbvqd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 460AE10EB67; Wed, 29 May 2024 20:24:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717014252; x=1748550252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IrZHmN2sobT+ghuBH2ewOlpXrfO6oAPOWALjSJ5VXO8=; b=XB9kbvqdtLysMIfW1AAgKCAitrLBDHRjAQe5VXDRZA+rNMofyjJba9ys 3BsiG5vwyMoQ2zPRbsSah1yGkTdmd0r/P80cwe7dn8XgAllWqN0eZROsO houh0oMzHIB1fdfuc4JRgoqj9PKAMGk6G3/rIrw7S9+4KK3hUDpC1JjS9 dlErDRqF+KJKsFWiA1DatQh3/oxBmIondwSG8TrxnucsZmuWXkqHFsSf8 vT9lp+Xd0zcaCG6bwOVqwyDqBx9c/xQxiJk9lYQEBXBiADF1a2MkBGKEN siDyqYykYZm7oRFwqJzw7Q1abbqnIRC5uenh8MVrHRttU0lGiQHw/LFqt A==; X-CSE-ConnectionGUID: 4ZE3T6nBTKe5VyhVNkzBWQ== X-CSE-MsgGUID: CR+hBCSXRGun/oL4GM9d/w== X-IronPort-AV: E=McAfee;i="6600,9927,11087"; a="13397242" X-IronPort-AV: E=Sophos;i="6.08,199,1712646000"; d="scan'208";a="13397242" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 13:24:11 -0700 X-CSE-ConnectionGUID: attszN9aQjqhXIanXeWWkA== X-CSE-MsgGUID: iXHXoKOtTuWn1DsbYvNdCA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,199,1712646000"; d="scan'208";a="66759984" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by fmviesa001.fm.intel.com with ESMTP; 29 May 2024 13:24:05 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= , Maxime Ripard , Ankit Nautiyal Subject: [PATCH v7 3/6] drm/display: Add missing aux less alpm wake related bits Date: Thu, 30 May 2024 01:37:39 +0530 Message-Id: <20240529200742.1694401-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20240529200742.1694401-1-animesh.manna@intel.com> References: <20240529200742.1694401-1-animesh.manna@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Jouni Högander eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Acked-by: Maxime Ripard Reviewed-by: Ankit Nautiyal Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 79bde372b152..f246fa03a3cb 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -232,6 +232,8 @@ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) @@ -684,7 +686,8 @@ #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE (1 << 0) -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)