| Message ID | 20240530-msm-drm-dsc-dsi-video-upstream-4-v6-3-2ab1d334c657@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC support to DSI video panel | expand |
On 5/29/2024 10:56 PM, Jun Nie wrote: > Enable compression bit in cfg2 register for DSC in the DSI case > per hardware version. > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Hi Jun, LGTM Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Thanks, Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++++++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++- > 3 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index 925ec6ada0e1..f2aab3e7c783 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -307,7 +307,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > > spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); > phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, > - &timing_params, fmt); > + &timing_params, fmt, > + phys_enc->dpu_kms->catalog->mdss_ver); > phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); > > /* setup which pp blk will connect to this intf */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index f97221423249..fa6debda0774 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -98,7 +98,8 @@ > > static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_timing_params *p, > - const struct msm_format *fmt) > + const struct msm_format *fmt, > + const struct dpu_mdss_version *mdss_ver) > { > struct dpu_hw_blk_reg_map *c = &intf->hw; > u32 hsync_period, vsync_period; > @@ -177,6 +178,11 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > if (p->wide_bus_en && !dp_intf) > data_width = p->width >> 1; > > + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ > + if (p->compression_en && !dp_intf && > + mdss_ver->core_major_ver >= 7) > + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; > + > hsync_data_start_x = hsync_start_x; > hsync_data_end_x = hsync_start_x + data_width - 1; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h > index f9015c67a574..ef947bf77693 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h > @@ -81,7 +81,8 @@ struct dpu_hw_intf_cmd_mode_cfg { > struct dpu_hw_intf_ops { > void (*setup_timing_gen)(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_timing_params *p, > - const struct msm_format *fmt); > + const struct msm_format *fmt, > + const struct dpu_mdss_version *mdss_ver); > > void (*setup_prg_fetch)(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_prog_fetch *fetch); > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 925ec6ada0e1..f2aab3e7c783 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -307,7 +307,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, - &timing_params, fmt); + &timing_params, fmt, + phys_enc->dpu_kms->catalog->mdss_ver); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); /* setup which pp blk will connect to this intf */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index f97221423249..fa6debda0774 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -98,7 +98,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt) + const struct msm_format *fmt, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_blk_reg_map *c = &intf->hw; u32 hsync_period, vsync_period; @@ -177,6 +178,11 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, if (p->wide_bus_en && !dp_intf) data_width = p->width >> 1; + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ + if (p->compression_en && !dp_intf && + mdss_ver->core_major_ver >= 7) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index f9015c67a574..ef947bf77693 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -81,7 +81,8 @@ struct dpu_hw_intf_cmd_mode_cfg { struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt); + const struct msm_format *fmt, + const struct dpu_mdss_version *mdss_ver); void (*setup_prg_fetch)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_prog_fetch *fetch);