From patchwork Thu May 30 08:35:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 13679912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 922D2C27C43 for ; Thu, 30 May 2024 08:35:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E86E810F45C; Thu, 30 May 2024 08:35:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="jfBCNrct"; dkim-atps=neutral Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7F67310E7C1 for ; Thu, 30 May 2024 08:35:24 +0000 (UTC) Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1f44b42e9a6so5156505ad.0 for ; Thu, 30 May 2024 01:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1717058124; x=1717662924; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ojWQ0b2MWifneyP6SWllMlL0oJitBi3xbuigAJTyN5g=; b=jfBCNrctjrzhaeqKsydsJ/ArgCbYOUdhssFVLcCN/Y/4muDnFwIAlQdbYmA7Amh7OC NhBfaQjCMiC7Zq00Ct+I501qfqUU/1G+gtGok2UyB1S9/R0pvCDo3BzmI1UWoHrhwjM0 pwxoilBGcmzl12LKd6mjywsfnMOMrvnFRKLMw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717058124; x=1717662924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ojWQ0b2MWifneyP6SWllMlL0oJitBi3xbuigAJTyN5g=; b=wMyxltR2tc0Hj4rOnx5GWwFcz+X42+KhlTjygsUbWx9f3jYWPKTrOjajX6ueBMBmqZ jivJY9MlqOLUI0OSLeUviYGR0Ed6TDgu0PmziOdtBBrkxfnV4wg7clApXQO1OszxBCLq jUQzG/pEhBsH0HkvnrWK5Wc3aGLYwqcFKhmS4FRIF9xj5MOQFv8XzSOuHrTI3eGytk/T W+OBODC62EEv4QVqCb59u7iVtqUBSoogEBa+srMo8oI8rdWxkog8MVCjO3peVpLjvy0Q +w/PvYw9c5wo1bZ0QTez41EJlLIkQ5g2+ALeZBPeU3b9o7o3gqzFUtD9JPxn6iX2a9QI rTjw== X-Forwarded-Encrypted: i=1; AJvYcCU9FROO1YhDquSYSfczhnjhJ6jE443Ohu9DeHC3Ybnb4rGkozQUFkhwQ+bdADkfpbhlbzChbts7UVVtr50YI8DDmpQQVmTiY46BaGp5pvDS X-Gm-Message-State: AOJu0YxcgFGJlYQW1Hf1rOa0WKGha3GB2yEZRGAyvSLMkW5pWmvpnJa1 Dweta/Y/nKachFaFRJDkfUap8qEP8YAgtfDxYosb9kmYNxLnlENsxE89UEC3+A== X-Google-Smtp-Source: AGHT+IGtD/EP0lwVmYxNyzuz01IBLVY6csgHPTcXqWU5CemCG3sK1VS5I0qtjDvBKandh/VKDc1VCA== X-Received: by 2002:a17:902:e810:b0:1e4:9c2f:d343 with SMTP id d9443c01a7336-1f6193fad6fmr15805455ad.7.1717058123772; Thu, 30 May 2024 01:35:23 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:65f0:63a9:90bb:50b8]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f617390fe7sm10950635ad.146.2024.05.30.01.35.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 01:35:23 -0700 (PDT) From: Chen-Yu Tsai To: Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: mediatek: Add mt8173 mfgtop Date: Thu, 30 May 2024 16:35:00 +0800 Message-ID: <20240530083513.4135052-2-wenst@chromium.org> X-Mailer: git-send-email 2.45.1.288.g0e0cd299f1-goog In-Reply-To: <20240530083513.4135052-1-wenst@chromium.org> References: <20240530083513.4135052-1-wenst@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP in the datasheet, that contains clock gates, some power sequence signal delays, and other unknown registers that get toggled when the GPU is powered on. The clock gates are exposed as clocks provided by a clock controller, while the power sequencing bits are exposed as one singular power domain. Signed-off-by: Chen-Yu Tsai Reviewed-by: Conor Dooley --- .../clock/mediatek,mt8173-mfgtop.yaml | 71 +++++++++++++++++++ include/dt-bindings/clock/mt8173-clk.h | 7 ++ 2 files changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml new file mode 100644 index 000000000000..03c3c1f8cf75 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8173 MFG TOP controller + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MFG TOP glue layer controls various signals going to the MFG (GPU) + block on the MT8173. + +properties: + compatible: + const: mediatek,mt8173-mfgtop + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: sys + - const: mem + - const: core + - const: clk26m + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + mfgtop: clock-controller@13fff000 { + compatible = "mediatek,mt8173-mfgtop"; + reg = <0x13fff000 0x1000>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>, + <&topckgen CLK_TOP_MEM_MFG_IN_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&clk26m>; + clock-names = "sys", "mem", "core", "clk26m"; + power-domains = <&spm MT8173_POWER_DOMAIN_MFG>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 3d00c98b9654..89e982f771db 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -243,6 +243,13 @@ #define CLK_IMG_FD 7 #define CLK_IMG_NR_CLK 8 +/* MFG_SYS */ + +#define CLK_MFG_AXI 0 +#define CLK_MFG_MEM 1 +#define CLK_MFG_G3D 2 +#define CLK_MFG_26M 3 + /* MM_SYS */ #define CLK_MM_SMI_COMMON 1