| Message ID | 20240623110753.141400-3-quic_akhilpo@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support for Adreno X1-85 GPU | expand |
On Sun, Jun 23, 2024 at 04:36:29PM GMT, Akhil P Oommen wrote: > Add support in drm/msm driver for the Adreno X185 gpu found in > Snapdragon X1 Elite chipset. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > */ > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > + if (adreno_is_x185(adreno_gpu)) { > + chipid = 0x7050001; > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > if (!pri_count) > return -EINVAL; > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > - if (IS_ERR(sec)) > - return PTR_ERR(sec); > + /* > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > + * to regular mx rail if it is missing Can we use compatibles / flags to detect this? > + */ > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > + return -EPROBE_DEFER; > + } else if (IS_ERR(sec)) { > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > + if (IS_ERR(sec)) > + return PTR_ERR(sec); > + } The following code might be slightly more idiomatic: sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER)) sec = cmd_db_read_aux_data("mx.lvl", &sec_count); if (IS_ERR(sec)) return PTR_ERR(sec); > > sec_count >>= 1; > if (!sec_count) > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 973872ad0474..97837f7f2a40 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > count = ARRAY_SIZE(a660_protect); > count_max = 48; > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > - } else if (adreno_is_a730(adreno_gpu) || > - adreno_is_a740(adreno_gpu) || > - adreno_is_a750(adreno_gpu)) { > + } else if (adreno_is_a7xx(adreno_gpu)) { > regs = a730_protect; > count = ARRAY_SIZE(a730_protect); > count_max = 48; > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > /* Set weights for bicubic filtering */ > - if (adreno_is_a650_family(adreno_gpu)) { > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, > 0x3fe05ff4); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index c3703a51287b..139c7d828749 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { > .zapfw = "a740_zap.mdt", > .hwcg = a740_hwcg, > .address_space_size = SZ_16G, > + }, { > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ > + .family = ADRENO_7XX_GEN2, > + .fw = { > + [ADRENO_FW_SQE] = "gen70500_sqe.fw", > + [ADRENO_FW_GMU] = "gen70500_gmu.bin", > + }, > + .gmem = 3 * SZ_1M, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > + ADRENO_QUIRK_HAS_HW_APRIV, > + .init = a6xx_gpu_init, > + .hwcg = a740_hwcg, > + .address_space_size = SZ_16G, Please rebase on top of https://lore.kernel.org/dri-devel/20240618164303.66615-1-robdclark@gmail.com/ > }, { > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > .family = ADRENO_7XX_GEN3, > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 77526892eb8c..d9ea8e0f6ad5 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) > return gpu->info->chip_ids[0] == 0x43051401; > } > > +static inline int adreno_is_x185(struct adreno_gpu *gpu) > +{ > + return gpu->info->chip_ids[0] == 0x43050c01; > +} > + > static inline int adreno_is_a740_family(struct adreno_gpu *gpu) > { > if (WARN_ON_ONCE(!gpu->info)) > -- > 2.45.1 >
On 6/23/24 13:06, Akhil P Oommen wrote: > Add support in drm/msm driver for the Adreno X185 gpu found in > Snapdragon X1 Elite chipset. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > */ > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > + if (adreno_is_x185(adreno_gpu)) { > + chipid = 0x7050001; What's wrong with using the logic below? > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > if (!pri_count) > return -EINVAL; > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > - if (IS_ERR(sec)) > - return PTR_ERR(sec); > + /* > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > + * to regular mx rail if it is missing > + */ > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > + return -EPROBE_DEFER; > + } else if (IS_ERR(sec)) { > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > + if (IS_ERR(sec)) > + return PTR_ERR(sec); > + } I assume GMXC would always be used if present, although please use the approach Dmitry suggested The rest looks good! Konrad
On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > Add support in drm/msm driver for the Adreno X185 gpu found in > Snapdragon X1 Elite chipset. > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > 4 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > */ > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > + if (adreno_is_x185(adreno_gpu)) { > + chipid = 0x7050001; > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > if (!pri_count) > return -EINVAL; > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > - if (IS_ERR(sec)) > - return PTR_ERR(sec); > + /* > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > + * to regular mx rail if it is missing > + */ > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > + return -EPROBE_DEFER; > + } else if (IS_ERR(sec)) { > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > + if (IS_ERR(sec)) > + return PTR_ERR(sec); > + } > > sec_count >>= 1; > if (!sec_count) > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 973872ad0474..97837f7f2a40 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > count = ARRAY_SIZE(a660_protect); > count_max = 48; > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > - } else if (adreno_is_a730(adreno_gpu) || > - adreno_is_a740(adreno_gpu) || > - adreno_is_a750(adreno_gpu)) { > + } else if (adreno_is_a7xx(adreno_gpu)) { > regs = a730_protect; > count = ARRAY_SIZE(a730_protect); > count_max = 48; > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > /* Set weights for bicubic filtering */ > - if (adreno_is_a650_family(adreno_gpu)) { > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, > 0x3fe05ff4); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index c3703a51287b..139c7d828749 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { > .zapfw = "a740_zap.mdt", > .hwcg = a740_hwcg, > .address_space_size = SZ_16G, > + }, { > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ > + .family = ADRENO_7XX_GEN2, > + .fw = { > + [ADRENO_FW_SQE] = "gen70500_sqe.fw", > + [ADRENO_FW_GMU] = "gen70500_gmu.bin", > + }, > + .gmem = 3 * SZ_1M, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > + ADRENO_QUIRK_HAS_HW_APRIV, > + .init = a6xx_gpu_init, > + .hwcg = a740_hwcg, > + .address_space_size = SZ_16G, I'm kinda thinking we should drop the address_space_size and add instead ADRENO_QUIRK_4G or something along those lines, since there are devices with 32 or 64G (a690 is incorrect in this way too) BR, -R > }, { > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > .family = ADRENO_7XX_GEN3, > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 77526892eb8c..d9ea8e0f6ad5 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) > return gpu->info->chip_ids[0] == 0x43051401; > } > > +static inline int adreno_is_x185(struct adreno_gpu *gpu) > +{ > + return gpu->info->chip_ids[0] == 0x43050c01; > +} > + > static inline int adreno_is_a740_family(struct adreno_gpu *gpu) > { > if (WARN_ON_ONCE(!gpu->info)) > -- > 2.45.1 >
On Mon, Jun 24, 2024 at 7:25 AM Rob Clark <robdclark@gmail.com> wrote: > > On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > > > Add support in drm/msm driver for the Adreno X185 gpu found in > > Snapdragon X1 Elite chipset. > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > --- > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > */ > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > > > + if (adreno_is_x185(adreno_gpu)) { > > + chipid = 0x7050001; > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > if (!pri_count) > > return -EINVAL; > > > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > - if (IS_ERR(sec)) > > - return PTR_ERR(sec); > > + /* > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > + * to regular mx rail if it is missing > > + */ > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > + return -EPROBE_DEFER; > > + } else if (IS_ERR(sec)) { > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > + if (IS_ERR(sec)) > > + return PTR_ERR(sec); > > + } > > > > sec_count >>= 1; > > if (!sec_count) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > index 973872ad0474..97837f7f2a40 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > > count = ARRAY_SIZE(a660_protect); > > count_max = 48; > > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > > - } else if (adreno_is_a730(adreno_gpu) || > > - adreno_is_a740(adreno_gpu) || > > - adreno_is_a750(adreno_gpu)) { > > + } else if (adreno_is_a7xx(adreno_gpu)) { > > regs = a730_protect; > > count = ARRAY_SIZE(a730_protect); > > count_max = 48; > > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) > > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > > > /* Set weights for bicubic filtering */ > > - if (adreno_is_a650_family(adreno_gpu)) { > > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, > > 0x3fe05ff4); > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > > index c3703a51287b..139c7d828749 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { > > .zapfw = "a740_zap.mdt", > > .hwcg = a740_hwcg, > > .address_space_size = SZ_16G, > > + }, { > > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ > > + .family = ADRENO_7XX_GEN2, > > + .fw = { > > + [ADRENO_FW_SQE] = "gen70500_sqe.fw", > > + [ADRENO_FW_GMU] = "gen70500_gmu.bin", > > + }, > > + .gmem = 3 * SZ_1M, > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > > + ADRENO_QUIRK_HAS_HW_APRIV, > > + .init = a6xx_gpu_init, > > + .hwcg = a740_hwcg, > > + .address_space_size = SZ_16G, > > I'm kinda thinking we should drop the address_space_size and add > instead ADRENO_QUIRK_4G or something along those lines, since there > are devices with 32 or 64G or alternatively put in a correct address_space_size (I guess 2^^48 or 2^^56 ?) BR, -R > (a690 is incorrect in this way too) > > BR, > -R > > > }, { > > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > > .family = ADRENO_7XX_GEN3, > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > index 77526892eb8c..d9ea8e0f6ad5 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) > > return gpu->info->chip_ids[0] == 0x43051401; > > } > > > > +static inline int adreno_is_x185(struct adreno_gpu *gpu) > > +{ > > + return gpu->info->chip_ids[0] == 0x43050c01; > > +} > > + > > static inline int adreno_is_a740_family(struct adreno_gpu *gpu) > > { > > if (WARN_ON_ONCE(!gpu->info)) > > -- > > 2.45.1 > >
On Mon, Jun 24, 2024 at 12:21:30AM +0300, Dmitry Baryshkov wrote: > On Sun, Jun 23, 2024 at 04:36:29PM GMT, Akhil P Oommen wrote: > > Add support in drm/msm driver for the Adreno X185 gpu found in > > Snapdragon X1 Elite chipset. > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > --- > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > */ > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > > > + if (adreno_is_x185(adreno_gpu)) { > > + chipid = 0x7050001; > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > if (!pri_count) > > return -EINVAL; > > > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > - if (IS_ERR(sec)) > > - return PTR_ERR(sec); > > + /* > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > + * to regular mx rail if it is missing > > Can we use compatibles / flags to detect this? I prefer the current approach so that we don't need to keep adding checks here for future targets. If gmxc is prefer, we have to use that in all targets. > > > + */ > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > + return -EPROBE_DEFER; > > + } else if (IS_ERR(sec)) { > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > + if (IS_ERR(sec)) > > + return PTR_ERR(sec); > > + } > > The following code might be slightly more idiomatic: > > sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER)) > sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > if (IS_ERR(sec)) > return PTR_ERR(sec); > Ack. This is neater! > > > > > sec_count >>= 1; > > if (!sec_count) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > index 973872ad0474..97837f7f2a40 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > > count = ARRAY_SIZE(a660_protect); > > count_max = 48; > > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > > - } else if (adreno_is_a730(adreno_gpu) || > > - adreno_is_a740(adreno_gpu) || > > - adreno_is_a750(adreno_gpu)) { > > + } else if (adreno_is_a7xx(adreno_gpu)) { > > regs = a730_protect; > > count = ARRAY_SIZE(a730_protect); > > count_max = 48; > > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) > > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > > > /* Set weights for bicubic filtering */ > > - if (adreno_is_a650_family(adreno_gpu)) { > > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, > > 0x3fe05ff4); > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > > index c3703a51287b..139c7d828749 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { > > .zapfw = "a740_zap.mdt", > > .hwcg = a740_hwcg, > > .address_space_size = SZ_16G, > > + }, { > > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ > > + .family = ADRENO_7XX_GEN2, > > + .fw = { > > + [ADRENO_FW_SQE] = "gen70500_sqe.fw", > > + [ADRENO_FW_GMU] = "gen70500_gmu.bin", > > + }, > > + .gmem = 3 * SZ_1M, > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > > + ADRENO_QUIRK_HAS_HW_APRIV, > > + .init = a6xx_gpu_init, > > + .hwcg = a740_hwcg, > > + .address_space_size = SZ_16G, > > Please rebase on top of https://lore.kernel.org/dri-devel/20240618164303.66615-1-robdclark@gmail.com/ Ack. -Akhil. > > > }, { > > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > > .family = ADRENO_7XX_GEN3, > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > index 77526892eb8c..d9ea8e0f6ad5 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) > > return gpu->info->chip_ids[0] == 0x43051401; > > } > > > > +static inline int adreno_is_x185(struct adreno_gpu *gpu) > > +{ > > + return gpu->info->chip_ids[0] == 0x43050c01; > > +} > > + > > static inline int adreno_is_a740_family(struct adreno_gpu *gpu) > > { > > if (WARN_ON_ONCE(!gpu->info)) > > -- > > 2.45.1 > > > > -- > With best wishes > Dmitry
On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: > > > On 6/23/24 13:06, Akhil P Oommen wrote: > > Add support in drm/msm driver for the Adreno X185 gpu found in > > Snapdragon X1 Elite chipset. > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > --- > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > */ > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > + if (adreno_is_x185(adreno_gpu)) { > > + chipid = 0x7050001; > > What's wrong with using the logic below? patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the changes in the chipid scheme within the a7x family, this is a bit confusing. I will try to improve here in another series. > > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > if (!pri_count) > > return -EINVAL; > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > - if (IS_ERR(sec)) > > - return PTR_ERR(sec); > > + /* > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > + * to regular mx rail if it is missing > > + */ > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > + return -EPROBE_DEFER; > > + } else if (IS_ERR(sec)) { > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > + if (IS_ERR(sec)) > > + return PTR_ERR(sec); > > + } > > I assume GMXC would always be used if present, although please use the > approach Dmitry suggested Correct. -Akhil > > > The rest looks good! > > Konrad
On 26.06.2024 10:24 AM, Akhil P Oommen wrote: > On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: >> >> >> On 6/23/24 13:06, Akhil P Oommen wrote: >>> Add support in drm/msm driver for the Adreno X185 gpu found in >>> Snapdragon X1 Elite chipset. >>> >>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>> --- >>> >>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- >>> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ >>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >>> 4 files changed, 36 insertions(+), 8 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> index 0e3dfd4c2bc8..168a4bddfaf2 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>> @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) >>> */ >>> gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); >>> + if (adreno_is_x185(adreno_gpu)) { >>> + chipid = 0x7050001; >> >> What's wrong with using the logic below? > > patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the > changes in the chipid scheme within the a7x family, this is a bit > confusing. I will try to improve here in another series. Ohh I overlooked this.. sounds a bit unfortunate.. Seems like it doesn't really fit the "else" branch anyway, let's keep it for now then Konrad
On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: > > > > > > On 6/23/24 13:06, Akhil P Oommen wrote: > > > Add support in drm/msm driver for the Adreno X185 gpu found in > > > Snapdragon X1 Elite chipset. > > > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > > --- > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > > */ > > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > > + if (adreno_is_x185(adreno_gpu)) { > > > + chipid = 0x7050001; > > > > What's wrong with using the logic below? > > patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the > changes in the chipid scheme within the a7x family, this is a bit > confusing. I will try to improve here in another series. I'm thinking we should just add gmu_chipid to struct a6xx_info, tbh Maybe to start with, we can fall back to the existing logic if a6xx_info::gmu_chipid is zero so we don't have to add it for _every_ a6xx/a7xx BR, -R > > > > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > > if (!pri_count) > > > return -EINVAL; > > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > - if (IS_ERR(sec)) > > > - return PTR_ERR(sec); > > > + /* > > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > > + * to regular mx rail if it is missing > > > + */ > > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > > + return -EPROBE_DEFER; > > > + } else if (IS_ERR(sec)) { > > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > + if (IS_ERR(sec)) > > > + return PTR_ERR(sec); > > > + } > > > > I assume GMXC would always be used if present, although please use the > > approach Dmitry suggested > > Correct. > > -Akhil > > > > > > The rest looks good! > > > > Konrad
On Mon, Jun 24, 2024 at 07:28:06AM -0700, Rob Clark wrote: > On Mon, Jun 24, 2024 at 7:25 AM Rob Clark <robdclark@gmail.com> wrote: > > > > On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > > > > > Add support in drm/msm driver for the Adreno X185 gpu found in > > > Snapdragon X1 Elite chipset. > > > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > > --- > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > > */ > > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > > > > > + if (adreno_is_x185(adreno_gpu)) { > > > + chipid = 0x7050001; > > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > > > > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > > if (!pri_count) > > > return -EINVAL; > > > > > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > - if (IS_ERR(sec)) > > > - return PTR_ERR(sec); > > > + /* > > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > > + * to regular mx rail if it is missing > > > + */ > > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > > + return -EPROBE_DEFER; > > > + } else if (IS_ERR(sec)) { > > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > + if (IS_ERR(sec)) > > > + return PTR_ERR(sec); > > > + } > > > > > > sec_count >>= 1; > > > if (!sec_count) > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > index 973872ad0474..97837f7f2a40 100644 > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > > > count = ARRAY_SIZE(a660_protect); > > > count_max = 48; > > > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > > > - } else if (adreno_is_a730(adreno_gpu) || > > > - adreno_is_a740(adreno_gpu) || > > > - adreno_is_a750(adreno_gpu)) { > > > + } else if (adreno_is_a7xx(adreno_gpu)) { > > > regs = a730_protect; > > > count = ARRAY_SIZE(a730_protect); > > > count_max = 48; > > > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) > > > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > > > > > /* Set weights for bicubic filtering */ > > > - if (adreno_is_a650_family(adreno_gpu)) { > > > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { > > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); > > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, > > > 0x3fe05ff4); > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > > > index c3703a51287b..139c7d828749 100644 > > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > > > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { > > > .zapfw = "a740_zap.mdt", > > > .hwcg = a740_hwcg, > > > .address_space_size = SZ_16G, > > > + }, { > > > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ > > > + .family = ADRENO_7XX_GEN2, > > > + .fw = { > > > + [ADRENO_FW_SQE] = "gen70500_sqe.fw", > > > + [ADRENO_FW_GMU] = "gen70500_gmu.bin", > > > + }, > > > + .gmem = 3 * SZ_1M, > > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > > > + ADRENO_QUIRK_HAS_HW_APRIV, > > > + .init = a6xx_gpu_init, > > > + .hwcg = a740_hwcg, > > > + .address_space_size = SZ_16G, > > > > I'm kinda thinking we should drop the address_space_size and add > > instead ADRENO_QUIRK_4G or something along those lines, since there > > are devices with 32 or 64G > > or alternatively put in a correct address_space_size (I guess 2^^48 or 2^^56 ?) Although I don't see any reason why the end address couldn't be the 'ttbr0/1 split address', we can keep 256GB as AS size for now. I will check this further and see if we can have a general logic for non-a630_family. -Akhil > > BR, > -R > > > (a690 is incorrect in this way too) > > > > BR, > > -R > > > > > }, { > > > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > > > .family = ADRENO_7XX_GEN3, > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > > index 77526892eb8c..d9ea8e0f6ad5 100644 > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) > > > return gpu->info->chip_ids[0] == 0x43051401; > > > } > > > > > > +static inline int adreno_is_x185(struct adreno_gpu *gpu) > > > +{ > > > + return gpu->info->chip_ids[0] == 0x43050c01; > > > +} > > > + > > > static inline int adreno_is_a740_family(struct adreno_gpu *gpu) > > > { > > > if (WARN_ON_ONCE(!gpu->info)) > > > -- > > > 2.45.1 > > >
On Wed, Jun 26, 2024 at 11:43:08AM -0700, Rob Clark wrote: > On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > > > On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: > > > > > > > > > On 6/23/24 13:06, Akhil P Oommen wrote: > > > > Add support in drm/msm driver for the Adreno X185 gpu found in > > > > Snapdragon X1 Elite chipset. > > > > > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > > > --- > > > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > > > */ > > > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > > > + if (adreno_is_x185(adreno_gpu)) { > > > > + chipid = 0x7050001; > > > > > > What's wrong with using the logic below? > > > > patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the > > changes in the chipid scheme within the a7x family, this is a bit > > confusing. I will try to improve here in another series. > > I'm thinking we should just add gmu_chipid to struct a6xx_info, tbh > > Maybe to start with, we can fall back to the existing logic if > a6xx_info::gmu_chipid is zero so we don't have to add it for _every_ > a6xx/a7xx Agree, I was thinking the same. -Akhil. > > BR, > -R > > > > > > > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > > > if (!pri_count) > > > > return -EINVAL; > > > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > > - if (IS_ERR(sec)) > > > > - return PTR_ERR(sec); > > > > + /* > > > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > > > + * to regular mx rail if it is missing > > > > + */ > > > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > > > + return -EPROBE_DEFER; > > > > + } else if (IS_ERR(sec)) { > > > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > > + if (IS_ERR(sec)) > > > > + return PTR_ERR(sec); > > > > + } > > > > > > I assume GMXC would always be used if present, although please use the > > > approach Dmitry suggested > > > > Correct. > > > > -Akhil > > > > > > > > > The rest looks good! > > > > > > Konrad
On Wed, Jun 26, 2024 at 1:49 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > On Mon, Jun 24, 2024 at 07:28:06AM -0700, Rob Clark wrote: > > On Mon, Jun 24, 2024 at 7:25 AM Rob Clark <robdclark@gmail.com> wrote: > > > > > > On Sun, Jun 23, 2024 at 4:08 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > > > > > > > > Add support in drm/msm driver for the Adreno X185 gpu found in > > > > Snapdragon X1 Elite chipset. > > > > > > > > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > > > > --- > > > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > > > > drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > > > > 4 files changed, 36 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > > index 0e3dfd4c2bc8..168a4bddfaf2 100644 > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > > > > @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > > > > */ > > > > gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > > > > > > > > + if (adreno_is_x185(adreno_gpu)) { > > > > + chipid = 0x7050001; > > > > /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ > > > > - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > > + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { > > > > /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ > > > > chipid = FIELD_PREP(GENMASK(31, 24), 0x7); > > > > > > > > @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, > > > > if (!pri_count) > > > > return -EINVAL; > > > > > > > > - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > > - if (IS_ERR(sec)) > > > > - return PTR_ERR(sec); > > > > + /* > > > > + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back > > > > + * to regular mx rail if it is missing > > > > + */ > > > > + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); > > > > + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { > > > > + return -EPROBE_DEFER; > > > > + } else if (IS_ERR(sec)) { > > > > + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); > > > > + if (IS_ERR(sec)) > > > > + return PTR_ERR(sec); > > > > + } > > > > > > > > sec_count >>= 1; > > > > if (!sec_count) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > index 973872ad0474..97837f7f2a40 100644 > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > > @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > > > > count = ARRAY_SIZE(a660_protect); > > > > count_max = 48; > > > > BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); > > > > - } else if (adreno_is_a730(adreno_gpu) || > > > > - adreno_is_a740(adreno_gpu) || > > > > - adreno_is_a750(adreno_gpu)) { > > > > + } else if (adreno_is_a7xx(adreno_gpu)) { > > > > regs = a730_protect; > > > > count = ARRAY_SIZE(a730_protect); > > > > count_max = 48; > > > > @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) > > > > gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); > > > > > > > > /* Set weights for bicubic filtering */ > > > > - if (adreno_is_a650_family(adreno_gpu)) { > > > > + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { > > > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); > > > > gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, > > > > 0x3fe05ff4); > > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > > > > index c3703a51287b..139c7d828749 100644 > > > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > > > > @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { > > > > .zapfw = "a740_zap.mdt", > > > > .hwcg = a740_hwcg, > > > > .address_space_size = SZ_16G, > > > > + }, { > > > > + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ > > > > + .family = ADRENO_7XX_GEN2, > > > > + .fw = { > > > > + [ADRENO_FW_SQE] = "gen70500_sqe.fw", > > > > + [ADRENO_FW_GMU] = "gen70500_gmu.bin", > > > > + }, > > > > + .gmem = 3 * SZ_1M, > > > > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > > > + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | > > > > + ADRENO_QUIRK_HAS_HW_APRIV, > > > > + .init = a6xx_gpu_init, > > > > + .hwcg = a740_hwcg, > > > > + .address_space_size = SZ_16G, > > > > > > I'm kinda thinking we should drop the address_space_size and add > > > instead ADRENO_QUIRK_4G or something along those lines, since there > > > are devices with 32 or 64G > > > > or alternatively put in a correct address_space_size (I guess 2^^48 or 2^^56 ?) > > Although I don't see any reason why the end address couldn't be the > 'ttbr0/1 split address', we can keep 256GB as AS size for now. I will > check this further and see if we can have a general logic for non-a630_family. Ahh, good point, I'd overlooked the ttbr0/ttrbr1 split. Since this is actually the userspace address space size it should be the size of ttbr0. For generations that do not support per-process pgtables, the address_space_size doesn't really matter (since in that case we don't allow userspace to allocate the iova's) BR, -R > -Akhil > > > > > BR, > > -R > > > > > (a690 is incorrect in this way too) > > > > > > BR, > > > -R > > > > > > > }, { > > > > .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ > > > > .family = ADRENO_7XX_GEN3, > > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > > > index 77526892eb8c..d9ea8e0f6ad5 100644 > > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > > > @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) > > > > return gpu->info->chip_ids[0] == 0x43051401; > > > > } > > > > > > > > +static inline int adreno_is_x185(struct adreno_gpu *gpu) > > > > +{ > > > > + return gpu->info->chip_ids[0] == 0x43050c01; > > > > +} > > > > + > > > > static inline int adreno_is_a740_family(struct adreno_gpu *gpu) > > > > { > > > > if (WARN_ON_ONCE(!gpu->info)) > > > > -- > > > > 2.45.1 > > > >
On 26.06.2024 8:43 PM, Rob Clark wrote: > On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: >> >> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: >>> >>> >>> On 6/23/24 13:06, Akhil P Oommen wrote: >>>> Add support in drm/msm driver for the Adreno X185 gpu found in >>>> Snapdragon X1 Elite chipset. >>>> >>>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>>> --- >>>> >>>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- >>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >>>> 4 files changed, 36 insertions(+), 8 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>> index 0e3dfd4c2bc8..168a4bddfaf2 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>> @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) >>>> */ >>>> gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); >>>> + if (adreno_is_x185(adreno_gpu)) { >>>> + chipid = 0x7050001; >>> >>> What's wrong with using the logic below? >> >> patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the >> changes in the chipid scheme within the a7x family, this is a bit >> confusing. I will try to improve here in another series. > > I'm thinking we should just add gmu_chipid to struct a6xx_info, tbh > > Maybe to start with, we can fall back to the existing logic if > a6xx_info::gmu_chipid is zero so we don't have to add it for _every_ > a6xx/a7xx If X185 is not the only occurence, I'd second this.. Konrad
On Wed, Jun 26, 2024 at 2:38 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > On 26.06.2024 8:43 PM, Rob Clark wrote: > > On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: > >> > >> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: > >>> > >>> > >>> On 6/23/24 13:06, Akhil P Oommen wrote: > >>>> Add support in drm/msm driver for the Adreno X185 gpu found in > >>>> Snapdragon X1 Elite chipset. > >>>> > >>>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > >>>> --- > >>>> > >>>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- > >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- > >>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ > >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ > >>>> 4 files changed, 36 insertions(+), 8 deletions(-) > >>>> > >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > >>>> index 0e3dfd4c2bc8..168a4bddfaf2 100644 > >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > >>>> @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) > >>>> */ > >>>> gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); > >>>> + if (adreno_is_x185(adreno_gpu)) { > >>>> + chipid = 0x7050001; > >>> > >>> What's wrong with using the logic below? > >> > >> patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the > >> changes in the chipid scheme within the a7x family, this is a bit > >> confusing. I will try to improve here in another series. > > > > I'm thinking we should just add gmu_chipid to struct a6xx_info, tbh > > > > Maybe to start with, we can fall back to the existing logic if > > a6xx_info::gmu_chipid is zero so we don't have to add it for _every_ > > a6xx/a7xx > > If X185 is not the only occurence, I'd second this.. basically all a7xx are "special" compared to the original logic, so we can start with using gmu_chipid for just a7xx BR, -R > Konrad
On 27.06.2024 12:32 AM, Rob Clark wrote: > On Wed, Jun 26, 2024 at 2:38 PM Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >> >> On 26.06.2024 8:43 PM, Rob Clark wrote: >>> On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote: >>>> >>>> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote: >>>>> >>>>> >>>>> On 6/23/24 13:06, Akhil P Oommen wrote: >>>>>> Add support in drm/msm driver for the Adreno X185 gpu found in >>>>>> Snapdragon X1 Elite chipset. >>>>>> >>>>>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >>>>>> --- >>>>>> >>>>>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- >>>>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- >>>>>> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ >>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ >>>>>> 4 files changed, 36 insertions(+), 8 deletions(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>>> index 0e3dfd4c2bc8..168a4bddfaf2 100644 >>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >>>>>> @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) >>>>>> */ >>>>>> gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); >>>>>> + if (adreno_is_x185(adreno_gpu)) { >>>>>> + chipid = 0x7050001; >>>>> >>>>> What's wrong with using the logic below? >>>> >>>> patchid is BITS(7, 0), not (15, 8) in the case of x185. Due to the >>>> changes in the chipid scheme within the a7x family, this is a bit >>>> confusing. I will try to improve here in another series. >>> >>> I'm thinking we should just add gmu_chipid to struct a6xx_info, tbh >>> >>> Maybe to start with, we can fall back to the existing logic if >>> a6xx_info::gmu_chipid is zero so we don't have to add it for _every_ >>> a6xx/a7xx >> >> If X185 is not the only occurence, I'd second this.. > > basically all a7xx are "special" compared to the original logic, so we > can start with using gmu_chipid for just a7xx That works Konrad
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 0e3dfd4c2bc8..168a4bddfaf2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -830,8 +830,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); + if (adreno_is_x185(adreno_gpu)) { + chipid = 0x7050001; /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ - if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { + } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ chipid = FIELD_PREP(GENMASK(31, 24), 0x7); @@ -1329,9 +1331,18 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, if (!pri_count) return -EINVAL; - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); - if (IS_ERR(sec)) - return PTR_ERR(sec); + /* + * Some targets have a separate gfx mxc rail. So try to read that first and then fall back + * to regular mx rail if it is missing + */ + sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); + if (PTR_ERR_OR_ZERO(sec) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(sec)) { + sec = cmd_db_read_aux_data("mx.lvl", &sec_count); + if (IS_ERR(sec)) + return PTR_ERR(sec); + } sec_count >>= 1; if (!sec_count) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 973872ad0474..97837f7f2a40 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1319,9 +1319,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || - adreno_is_a740(adreno_gpu) || - adreno_is_a750(adreno_gpu)) { + } else if (adreno_is_a7xx(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -1891,7 +1889,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); /* Set weights for bicubic filtering */ - if (adreno_is_a650_family(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 0x3fe05ff4); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c3703a51287b..139c7d828749 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -568,6 +568,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ + .family = ADRENO_7XX_GEN2, + .fw = { + [ADRENO_FW_SQE] = "gen70500_sqe.fw", + [ADRENO_FW_GMU] = "gen70500_gmu.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .hwcg = a740_hwcg, + .address_space_size = SZ_16G, }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family = ADRENO_7XX_GEN3, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..d9ea8e0f6ad5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -448,6 +448,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43051401; } +static inline int adreno_is_x185(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43050c01; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info))
Add support in drm/msm driver for the Adreno X185 gpu found in Snapdragon X1 Elite chipset. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 19 +++++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++---- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 4 files changed, 36 insertions(+), 8 deletions(-)