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([178.197.219.137]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4248179d3basm105465515e9.4.2024.06.23.05.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jun 2024 05:00:32 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 3/3] dt-bindings: display/msm/gpu: constrain reg/reg-names per variant Date: Sun, 23 Jun 2024 14:00:26 +0200 Message-ID: <20240623120026.44198-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> References: <20240623120026.44198-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" MMIO address space is known per each variant of Adreno GPU, so we can constrain the reg/reg-names entries for each variant. There is no DTS for A619, so that part is not accurate but could be corrected later. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/gpu.yaml | 87 +++++++++++++++++-- 1 file changed, 79 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index baea1946c65d..e83f13123fc9 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -130,6 +130,22 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + then: + properties: + reg: + minItems: 3 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc + - if: properties: compatible: @@ -164,6 +180,13 @@ allOf: minItems: 2 maxItems: 7 + reg: + maxItems: 1 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + required: - clocks - clock-names @@ -196,11 +219,12 @@ allOf: - const: xo description: GPUCC clocksource clock + reg: + maxItems: 1 + reg-names: - minItems: 1 items: - const: kgsl_3d0_reg_memory - - const: cx_dbgc required: - clocks @@ -217,12 +241,59 @@ allOf: clocks: false clock-names: false - reg-names: - minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-640.1 + - qcom,adreno-680.1 + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-619.0 + - qcom,adreno-630.2 + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-618.0 + - qcom,adreno-635.0 + - qcom,adreno-690.0 + - qcom,adreno-730.1 + then: + properties: + reg: + minItems: 3 + + reg-names: + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - |