| Message ID | 20240623143846.12603-2-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/6] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement | expand |
Am Sonntag, 23. Juni 2024, 16:38:34 CEST schrieb Marek Vasut: > Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the > Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and > pass it down the display pipeline to obtain exactly this frequency on input > into this bridge. > > The precise input frequency that matches the Pixel PLL frequency is > important for this bridge, as if the frequencies do not match, the > bridge does suffer VFIFO overruns or underruns. > > Signed-off-by: Marek Vasut <marex@denx.de> This changes actually changes the media_disp1_pix clock to match the configured PLL rate in the bridge. 147333000 instead of 148500000. Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> > --- > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: David Airlie <airlied@gmail.com> > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > Cc: Jonas Karlman <jonas@kwiboo.se> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Maxime Ripard <mripard@kernel.org> > Cc: Neil Armstrong <neil.armstrong@linaro.org> > Cc: Robert Foss <rfoss@kernel.org> > Cc: Thomas Zimmermann <tzimmermann@suse.de> > Cc: dri-devel@lists.freedesktop.org > Cc: kernel@dh-electronics.com > --- > V2: - Use mode clock as input into tc_pxl_pll_calc() to avoid > accumulating rounding error > V3: No change > --- > drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c > index cbb342d811ac3..20be21660ba76 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge, > struct drm_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > { > + struct tc_data *tc = bridge_to_tc(bridge); > + int adjusted_clock = 0; > + int ret; > + > + ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), > + crtc_state->mode.clock * 1000, > + &adjusted_clock, NULL); > + if (ret) > + return ret; > + > + crtc_state->adjusted_mode.clock = adjusted_clock / 1000; > + > /* DSI->DPI interface clock limitation: upto 100 MHz */ > if (crtc_state->adjusted_mode.clock > 100000) > return -EINVAL; > @@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge, > struct drm_crtc_state *crtc_state, > struct drm_connector_state *conn_state) > { > + struct tc_data *tc = bridge_to_tc(bridge); > + int adjusted_clock = 0; > + int ret; > + > + ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), > + crtc_state->mode.clock * 1000, > + &adjusted_clock, NULL); > + if (ret) > + return ret; > + > + crtc_state->adjusted_mode.clock = adjusted_clock / 1000; > + > /* DPI->(e)DP interface clock limitation: upto 154 MHz */ > if (crtc_state->adjusted_mode.clock > 154000) > return -EINVAL; >
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index cbb342d811ac3..20be21660ba76 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct tc_data *tc = bridge_to_tc(bridge); + int adjusted_clock = 0; + int ret; + + ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), + crtc_state->mode.clock * 1000, + &adjusted_clock, NULL); + if (ret) + return ret; + + crtc_state->adjusted_mode.clock = adjusted_clock / 1000; + /* DSI->DPI interface clock limitation: upto 100 MHz */ if (crtc_state->adjusted_mode.clock > 100000) return -EINVAL; @@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct tc_data *tc = bridge_to_tc(bridge); + int adjusted_clock = 0; + int ret; + + ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), + crtc_state->mode.clock * 1000, + &adjusted_clock, NULL); + if (ret) + return ret; + + crtc_state->adjusted_mode.clock = adjusted_clock / 1000; + /* DPI->(e)DP interface clock limitation: upto 154 MHz */ if (crtc_state->adjusted_mode.clock > 154000) return -EINVAL;
Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and pass it down the display pipeline to obtain exactly this frequency on input into this bridge. The precise input frequency that matches the Pixel PLL frequency is important for this bridge, as if the frequencies do not match, the bridge does suffer VFIFO overruns or underruns. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: David Airlie <airlied@gmail.com> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Jonas Karlman <jonas@kwiboo.se> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Robert Foss <rfoss@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: dri-devel@lists.freedesktop.org Cc: kernel@dh-electronics.com --- V2: - Use mode clock as input into tc_pxl_pll_calc() to avoid accumulating rounding error V3: No change --- drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)