diff mbox series

[v3,6/6] Revert "drm/bridge: tc358767: Set default CLRSIPO count"

Message ID 20240623143846.12603-6-marex@denx.de (mailing list archive)
State New, archived
Headers show
Series [v3,1/6] drm/bridge: tc358767: Split tc_pxl_pll_en() into parameter calculation and enablement | expand

Commit Message

Marek Vasut June 23, 2024, 2:38 p.m. UTC
This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.

With clock improvements in place, this seems to be no longer
necessary. Set the CLRSIPO to default setting recommended by
manufacturer.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: kernel@dh-electronics.com
---
V2: No change
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Alexander Stein June 24, 2024, 8:38 a.m. UTC | #1
Am Sonntag, 23. Juni 2024, 16:38:38 CEST schrieb Marek Vasut:
> This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0.
> 
> With clock improvements in place, this seems to be no longer
> necessary. Set the CLRSIPO to default setting recommended by
> manufacturer.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

Although calculation sheet indicates this depends on DSI-Timings, this
works as well.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> ---
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Neil Armstrong <neil.armstrong@linaro.org>
> Cc: Robert Foss <rfoss@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: kernel@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index 743bf1334923d..2b035a136a6e5 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1356,10 +1356,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc)
>  	u32 value;
>  	int ret;
>  
> -	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
> -	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
> +	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
> +	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
>  	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
>  	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
>  	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 743bf1334923d..2b035a136a6e5 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1356,10 +1356,10 @@  static int tc_dsi_rx_enable(struct tc_data *tc)
 	u32 value;
 	int ret;
 
-	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
-	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
-	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
-	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
+	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
 	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
 	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
 	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);