From patchwork Wed Jun 26 20:40:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 13713392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBC24C30653 for ; Wed, 26 Jun 2024 20:40:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA58010E223; Wed, 26 Jun 2024 20:40:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gwjEJ5on"; dkim-atps=neutral Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTPS id B800C10E15E; Wed, 26 Jun 2024 20:40:46 +0000 (UTC) Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-70df2135426so4660841a12.2; Wed, 26 Jun 2024 13:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719434446; x=1720039246; darn=lists.freedesktop.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uaTg9/B23waOI9zVmutPgK2+FneQd1nJivbxDxQ8kVQ=; b=gwjEJ5on9Kvj4K2ATuUJvFEGTKKwuS4KaVIax9sNRKWay3fqL12C25z6qPW1zUTYZf tQzrc0xF0PT0+oK04kHSWCdSaz50QK/12CKZ8RTj0jwYOgtjVtgA/BjE0YzH3v9VtOo7 Sf/eJ/Ulp5nw1ln3qDJ2NzO6gUe3Bt9P+BJi97gh19ZjtsB+FxQzG5QrUj/6m8f5Smbp K3ad15IHLay8h/HdM6L6rq4Ooa166Gqc+u4geMZC6tpWjxzk4o/jyhmzD7cKhMFefvmj gFHdjfWcyG1QRJLUw1ljIIKvtPl9VN/RU9GXFv0R9E9r5gv/+6t2v7fbtBxLSx8tg6bn IPbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719434446; x=1720039246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uaTg9/B23waOI9zVmutPgK2+FneQd1nJivbxDxQ8kVQ=; b=tTIohg2iTMS15I+a6z+hhSfZBXbI2/m5uvlzEU0xpFRbsFvhMP9IqnQp8bUASAf21T TnuVamRmxWWe/cwJQePejTmFZ5amLaKga6GJVGl0pKjBY3e24ZHttPwITnYxUfzC6HqI 7u9Sr/qYLUq4rlHrbRBi4KpFsrvMvjVI7ojdk1UM/VUqq6kovOHYItUoDmAk9A6moiMs VzQ+7y1e7cA5gBnOXZ6CBQikomFdT2qrePJSNYbdHr4bMVWMWvZxmzwQILCNaXwiYJXE S8KN80PCcamzm0u+5vgJcF8p+Cq6XBiq/RbcQ56SSbjHZZWlLdLwun0yP5KDSNjEZWQL 91eg== X-Forwarded-Encrypted: i=1; AJvYcCUscR9EhpGqwXaM8f4fMlfsKOVx61OFpBI8PgkVG46178qu6w2pQE7QdgbV40DyxqSo/MF6BXJxslTjECeG4Xue8aNjnSbwS0+v6yHoz+/6HbIN/bNNIr5su/BHfgYyAPTuuQpPH3tFEpZdrItv6Dpb X-Gm-Message-State: AOJu0YybReU9nKGtZKGE5h9sIZQ0jr/z1UzZ9pQ51zFJQ18TP/8TdvOG MIy0NpmudxfOHG3Vv8m2OuH0QMb02paS/JWl8zKi2tNv5NVS/eWq X-Google-Smtp-Source: AGHT+IF1OWXRmVAc7P/t2mo7Vtey9dDgaSNQaluXlN5oULC7q6DlJRy1fKAenx9cbqHNm6YYfgPHbA== X-Received: by 2002:a05:6a20:214a:b0:1be:c5f5:589 with SMTP id adf61e73a8af0-1bec5f50ae7mr1535396637.55.1719434445944; Wed, 26 Jun 2024 13:40:45 -0700 (PDT) Received: from localhost ([2a00:79e1:2e00:1301:e1c5:6354:b45d:8ffc]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fa1f39695bsm75150625ad.278.2024.06.26.13.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 13:40:45 -0700 (PDT) From: Rob Clark To: iommu@lists.linux.dev Cc: linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy , Rob Clark , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org (open list:DRM DRIVER for Qualcomm Adreno GPUs), freedreno@lists.freedesktop.org (open list:DRM DRIVER for Qualcomm Adreno GPUs), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 2/2] drm/msm: Extend gpu devcore dumps with pgtbl info Date: Wed, 26 Jun 2024 13:40:27 -0700 Message-ID: <20240626204033.255813-3-robdclark@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240626204033.255813-1-robdclark@gmail.com> References: <20240626204033.255813-1-robdclark@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Rob Clark In the case of iova fault triggered devcore dumps, include additional debug information based on what we think is the current page tables, including the TTBR0 value (which should match what we have in adreno_smmu_fault_info unless things have gone horribly wrong), and the pagetable entries traversed in the process of resolving the faulting iova. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 ++++++++++ drivers/gpu/drm/msm/msm_gpu.c | 9 +++++++++ drivers/gpu/drm/msm/msm_gpu.h | 8 ++++++++ drivers/gpu/drm/msm/msm_iommu.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 3 ++- 5 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 99661af8d941..422dae873b6b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -861,6 +861,16 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ"); drm_printf(p, " - type=%s\n", info->type); drm_printf(p, " - source=%s\n", info->block); + + /* Information extracted from what we think are the current + * pgtables. Hopefully the TTBR0 matches what we've extracted + * from the SMMU registers in smmu_info! + */ + drm_puts(p, "pgtable-fault-info:\n"); + drm_printf(p, " - ttbr0: %.16llx\n", (u64)info->pgtbl_ttbr0); + drm_printf(p, " - asid: %d\n", info->asid); + drm_printf(p, " - ptes: %.16llx %.16llx %.16llx %.16llx\n", + info->ptes[0], info->ptes[1], info->ptes[2], info->ptes[3]); } drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 3666b42b4ecd..bf2f8b2a7ccc 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -281,6 +281,15 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, if (submit) { int i; + if (state->fault_info.ttbr0) { + struct msm_gpu_fault_info *info = &state->fault_info; + struct msm_mmu *mmu = submit->aspace->mmu; + + msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0, + &info->asid); + msm_iommu_pagetable_walk(mmu, info->iova, info->ptes); + } + state->bos = kcalloc(submit->nr_bos, sizeof(struct msm_gpu_state_bo), GFP_KERNEL); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f02bb9956be..82e838ba8c80 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -101,6 +101,14 @@ struct msm_gpu_fault_info { int flags; const char *type; const char *block; + + /* Information about what we think/expect is the current SMMU state, + * for example expected_ttbr0 should match smmu_info.ttbr0 which + * was read back from SMMU registers. + */ + phys_addr_t pgtbl_ttbr0; + u64 ptes[4]; + int asid; }; /** diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index d5512037c38b..a235b0d0afb5 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -195,6 +195,31 @@ struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu) return &iommu->domain->geometry; } +int +msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova, uint64_t ptes[4]) +{ + struct msm_iommu_pagetable *pagetable; + struct io_pgtable_walk_data wd = {}; + int ret; + + if (mmu->type != MSM_MMU_IOMMU_PAGETABLE) + return -EINVAL; + + pagetable = to_pagetable(mmu); + + if (!pagetable->pgtbl_ops->pgtable_walk) + return -EINVAL; + + ret = pagetable->pgtbl_ops->pgtable_walk(pagetable->pgtbl_ops, iova, &wd); + if (ret) + return ret; + + for (int i = 0; i < ARRAY_SIZE(wd.ptes); i++) + ptes[i] = wd.ptes[i]; + + return 0; +} + static const struct msm_mmu_funcs pagetable_funcs = { .map = msm_iommu_pagetable_map, .unmap = msm_iommu_pagetable_unmap, diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 88af4f490881..96e509bd96a6 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -53,7 +53,8 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent); int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, - int *asid); + int *asid); +int msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova, uint64_t ptes[4]); struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu); #endif /* __MSM_MMU_H__ */