From patchwork Wed Jul 3 10:50:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Walklin X-Patchwork-Id: 13721994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39C30C2BD09 for ; Wed, 3 Jul 2024 10:55:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA4DB10E785; Wed, 3 Jul 2024 10:55:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=testtoast.com header.i=@testtoast.com header.b="Qz6qm/3Y"; dkim=pass (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="ubEULuJ1"; dkim-atps=neutral Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) by gabe.freedesktop.org (Postfix) with ESMTPS id 180D710E785 for ; Wed, 3 Jul 2024 10:55:28 +0000 (UTC) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailfhigh.nyi.internal (Postfix) with ESMTP id 796B41140376; Wed, 3 Jul 2024 06:55:27 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Wed, 03 Jul 2024 06:55:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=testtoast.com; h=cc:cc:content-transfer-encoding:content-type:date:date:from :from:in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=fm2; t=1720004127; x= 1720090527; bh=oCorl3qmSGKsy6vkckXLjG90/aRYhwkyp+JyaJ/Jtak=; b=Q z6qm/3YohxdFSxZZ0RIYEsfD3DnWBxiqM/H596Z5hoUV9K2JwbwkyKW54wlG7mPG eB6+rhzN3aDgZ+3rKX6hz6/NxmNxziRRj3bPYWmsqpg9/RGIlGjEadrX05xJXZn0 xbHxcLHG0aPVTapoFXn/E4vv5R3qUK8DxgWo+qmFehPTzA0aVQse7iykZrXqP0s4 Vqx6dGbPzEQJyBifLxBodm6lLYHdEIQWktEhLMicrZdJF72+3QEXHs9s7cpDEDfu Zi858FIt+kWMpHV4luQ/RRaLUm0mbesgGfAROkzcLWXZMseFsCrcHaETwIUCPeCS TQqLy9Xv+G0SRd2oVGRqA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1720004127; x= 1720090527; bh=oCorl3qmSGKsy6vkckXLjG90/aRYhwkyp+JyaJ/Jtak=; b=u bEULuJ1XzqmDBnYPG1wy6U4Ez+bWq72bwV0rWL8qk5r/PA2ypewOxbknmflvELgK R4IF+BhC6KcsPoKCMjbqLJ45sv6oMPCr3KNtT5dt6/8XK+4sWuWr2wdkdQ/oAhkN 2n4AMJLJRSAJWOu5r856JfY3G/Zvh8ssUsRCBFTIJaJX50d7xKWflSqHoiLoST+1 dd5j2Ma19AGIk8bzxWOh93/WC2txJUeYzAVUBmADDfFXH/knFpBgFJYD98hdyZbh 4GcSncLKMR1SVPsZBHafPCmbBCU75q1sNg6tNJHqF+aDrtR57AgB6Z1x2D7OzlNg fv84/mzSXx0UGzOgIIKTQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudejgdefgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefthigrnhcu hggrlhhklhhinhcuoehrhigrnhesthgvshhtthhorghsthdrtghomheqnecuggftrfgrth htvghrnhepffehieffgedtgfffjeetveegfeekleeileekveeuteffteetudffveegieei heetnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomheprh ihrghnsehtvghsthhtohgrshhtrdgtohhm X-ME-Proxy: Feedback-ID: idc0145fc:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 3 Jul 2024 06:55:21 -0400 (EDT) From: Ryan Walklin To: Maxime Ripard , Chen-Yu Tsai , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Daniel Vetter , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: Andre Przywara , Chris Morgan , John Watts , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Ryan Walklin Subject: [PATCH v2 02/23] drm: sun4i: de2/de3: Merge CSC functions into one Date: Wed, 3 Jul 2024 22:50:52 +1200 Message-ID: <20240703105454.41254-3-ryan@testtoast.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240703105454.41254-1-ryan@testtoast.com> References: <20240703105454.41254-1-ryan@testtoast.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Jernej Skrabec Merging both function into one lets this one decide on it's own if CSC should be enabled or not. Currently heuristics for that is pretty simple - enable it for YUV formats and disable for RGB. However, DE3 can have whole pipeline in RGB or YUV format. YUV pipeline will be supported in later commits. Signed-off-by: Jernej Skrabec Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara --- drivers/gpu/drm/sun4i/sun8i_csc.c | 89 ++++++++++---------------- drivers/gpu/drm/sun4i/sun8i_csc.h | 9 ++- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 11 +--- 3 files changed, 40 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c index 6ebd1c3aa3ab5..0dcbc0866ae82 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -107,23 +107,28 @@ static const u32 yuv2rgb_de3[2][3][12] = { }, }; -static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, - enum format_type fmt_type, - enum drm_color_encoding encoding, - enum drm_color_range range) +static void sun8i_csc_setup(struct regmap *map, u32 base, + enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) { + u32 base_reg, val; const u32 *table; - u32 base_reg; int i; table = yuv2rgb[range][encoding]; switch (fmt_type) { + case FORMAT_TYPE_RGB: + val = 0; + break; case FORMAT_TYPE_YUV: + val = SUN8I_CSC_CTRL_EN; base_reg = SUN8I_CSC_COEFF(base, 0); regmap_bulk_write(map, base_reg, table, 12); break; case FORMAT_TYPE_YVU: + val = SUN8I_CSC_CTRL_EN; for (i = 0; i < 12; i++) { if ((i & 3) == 1) base_reg = SUN8I_CSC_COEFF(base, i + 1); @@ -135,28 +140,37 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, } break; default: + val = 0; DRM_WARN("Wrong CSC mode specified.\n"); return; } + + regmap_write(map, SUN8I_CSC_CTRL(base), val); } -static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, - enum format_type fmt_type, - enum drm_color_encoding encoding, - enum drm_color_range range) +static void sun8i_de3_ccsc_setup(struct regmap *map, int layer, + enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) { + u32 addr, val, mask; const u32 *table; - u32 addr; int i; + mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); table = yuv2rgb_de3[range][encoding]; switch (fmt_type) { + case FORMAT_TYPE_RGB: + val = 0; + break; case FORMAT_TYPE_YUV: + val = mask; addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); regmap_bulk_write(map, addr, table, 12); break; case FORMAT_TYPE_YVU: + val = mask; for (i = 0; i < 12; i++) { if ((i & 3) == 1) addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, @@ -173,67 +187,30 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, } break; default: + val = 0; DRM_WARN("Wrong CSC mode specified.\n"); return; } -} - -static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable) -{ - u32 val; - - if (enable) - val = SUN8I_CSC_CTRL_EN; - else - val = 0; - - regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val); -} - -static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) -{ - u32 val, mask; - - mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); - - if (enable) - val = mask; - else - val = 0; regmap_update_bits(map, SUN50I_MIXER_BLEND_CSC_CTL(DE3_BLD_BASE), mask, val); } -void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, - enum format_type fmt_type, - enum drm_color_encoding encoding, - enum drm_color_range range) -{ - u32 base; - - if (mixer->cfg->is_de3) { - sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, - fmt_type, encoding, range); - return; - } - - base = ccsc_base[mixer->cfg->ccsc][layer]; - - sun8i_csc_set_coefficients(mixer->engine.regs, base, - fmt_type, encoding, range); -} - -void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) +void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range) { u32 base; if (mixer->cfg->is_de3) { - sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable); + sun8i_de3_ccsc_setup(mixer->engine.regs, layer, + fmt_type, encoding, range); return; } base = ccsc_base[mixer->cfg->ccsc][layer]; - sun8i_csc_enable(mixer->engine.regs, base, enable); + sun8i_csc_setup(mixer->engine.regs, base, + fmt_type, encoding, range); } diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h index 7322770f39f03..b7546e06e315c 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.h +++ b/drivers/gpu/drm/sun4i/sun8i_csc.h @@ -28,10 +28,9 @@ enum format_type { FORMAT_TYPE_YVU, }; -void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, - enum format_type fmt_type, - enum drm_color_encoding encoding, - enum drm_color_range range); -void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable); +void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer, + enum format_type fmt_type, + enum drm_color_encoding encoding, + enum drm_color_range range); #endif diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 76e2d3ec0a78c..6ee3790a2a812 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -281,14 +281,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val); fmt_type = sun8i_vi_layer_get_format_type(fmt); - if (fmt_type != FORMAT_TYPE_RGB) { - sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_type, - state->color_encoding, - state->color_range); - sun8i_csc_enable_ccsc(mixer, channel, true); - } else { - sun8i_csc_enable_ccsc(mixer, channel, false); - } + sun8i_csc_set_ccsc(mixer, channel, fmt_type, + state->color_encoding, + state->color_range); if (!fmt->is_yuv) val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;