diff mbox series

[01/10] dt-bindings: display: imx: Add some i.MX8qxp Display Controller processing units

Message ID 20240705090932.1880496-2-victor.liu@nxp.com (mailing list archive)
State New, archived
Headers show
Series Add Freescale i.MX8qxp Display Controller support | expand

Commit Message

Liu Ying July 5, 2024, 9:09 a.m. UTC
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces.

Document some processing units to support two display outputs.

ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend processing units
are in pixel engine.  FrameGen and TCon processing units are in display
engine.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 .../imx/fsl,imx8qxp-dc-constframe.yaml        |  51 +++++++
 .../display/imx/fsl,imx8qxp-dc-extdst.yaml    |  79 +++++++++++
 .../imx/fsl,imx8qxp-dc-fetchlayer.yaml        |  37 ++++++
 .../imx/fsl,imx8qxp-dc-fetchunit-common.yaml  | 125 ++++++++++++++++++
 .../display/imx/fsl,imx8qxp-dc-fetchwarp.yaml |  37 ++++++
 .../display/imx/fsl,imx8qxp-dc-framegen.yaml  |  71 ++++++++++
 .../imx/fsl,imx8qxp-dc-layerblend.yaml        |  46 +++++++
 .../display/imx/fsl,imx8qxp-dc-tcon.yaml      |  41 ++++++
 8 files changed, 487 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml

Comments

Krzysztof Kozlowski July 7, 2024, 1:58 p.m. UTC | #1
On 05/07/2024 11:09, Liu Ying wrote:
> Freescale i.MX8qxp Display Controller is implemented as construction set of
> building blocks with unified concept and standardized interfaces.
> 
> Document some processing units to support two display outputs.


> +maintainers:
> +  - Liu Ying <victor.liu@nxp.com>
> +
> +properties:
> +  compatible:
> +    const: fsl,imx8qxp-dc-tcon
> +
> +  reg:
> +    maxItems: 1
> +
> +  fsl,dc-tc-id:
> +    description: Timing Controller unit instance number

No instance numbering. This applies to your entire patchset.



Best regards,
Krzysztof
Liu Ying July 8, 2024, 6:30 a.m. UTC | #2
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>> building blocks with unified concept and standardized interfaces.
>>
>> Document some processing units to support two display outputs.
> 
> 
>> +maintainers:
>> +  - Liu Ying <victor.liu@nxp.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: fsl,imx8qxp-dc-tcon
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  fsl,dc-tc-id:
>> +    description: Timing Controller unit instance number
> 
> No instance numbering. This applies to your entire patchset.

Then, I'll call of_alias_get_id() from the drivers to get
instance number instead.

As i.MX8qm SoC embeds two Display Controllers, the alias
stem would contain the Display Controller instance
number, like "dc0-tcon" and "dc1-tcon".  Is this ok?

> 
> 
> 
> Best regards,
> Krzysztof
> 
>
Rob Herring July 8, 2024, 8:04 p.m. UTC | #3
On Mon, Jul 08, 2024 at 02:30:37PM +0800, Liu Ying wrote:
> On 07/07/2024, Krzysztof Kozlowski wrote:
> > On 05/07/2024 11:09, Liu Ying wrote:
> >> Freescale i.MX8qxp Display Controller is implemented as construction set of
> >> building blocks with unified concept and standardized interfaces.
> >>
> >> Document some processing units to support two display outputs.
> > 
> > 
> >> +maintainers:
> >> +  - Liu Ying <victor.liu@nxp.com>
> >> +
> >> +properties:
> >> +  compatible:
> >> +    const: fsl,imx8qxp-dc-tcon
> >> +
> >> +  reg:
> >> +    maxItems: 1
> >> +
> >> +  fsl,dc-tc-id:
> >> +    description: Timing Controller unit instance number
> > 
> > No instance numbering. This applies to your entire patchset.
> 
> Then, I'll call of_alias_get_id() from the drivers to get
> instance number instead.

Ideally, no.

> As i.MX8qm SoC embeds two Display Controllers, the alias
> stem would contain the Display Controller instance
> number, like "dc0-tcon" and "dc1-tcon".  Is this ok?

The format of aliases is fooN, so no. Aliases should also be generic 
rather than vendor specific.

If you need to describe the connection of components in the display 
pipeline, then use the graph binding.

Rob
Liu Ying July 9, 2024, 7:36 a.m. UTC | #4
On 07/09/2024, Rob Herring wrote:
> On Mon, Jul 08, 2024 at 02:30:37PM +0800, Liu Ying wrote:
>> On 07/07/2024, Krzysztof Kozlowski wrote:
>>> On 05/07/2024 11:09, Liu Ying wrote:
>>>> Freescale i.MX8qxp Display Controller is implemented as construction set of
>>>> building blocks with unified concept and standardized interfaces.
>>>>
>>>> Document some processing units to support two display outputs.
>>>
>>>
>>>> +maintainers:
>>>> +  - Liu Ying <victor.liu@nxp.com>
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: fsl,imx8qxp-dc-tcon
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  fsl,dc-tc-id:
>>>> +    description: Timing Controller unit instance number
>>>
>>> No instance numbering. This applies to your entire patchset.
>>
>> Then, I'll call of_alias_get_id() from the drivers to get
>> instance number instead.
> 
> Ideally, no.
> 
>> As i.MX8qm SoC embeds two Display Controllers, the alias
>> stem would contain the Display Controller instance
>> number, like "dc0-tcon" and "dc1-tcon".  Is this ok?
> 
> The format of aliases is fooN, so no. Aliases should also be generic 
> rather than vendor specific.
> 
> If you need to describe the connection of components in the display 
> pipeline, then use the graph binding.

I mentioned OF graph in the previous patch set discussion.

"
There are 50+ individual DPU internal units and 20+ unit types.
Do you really mean that each unit should be a separate device in
device tree and each unit type should have it's own compatible
string ? 


Almost all units have input/output ports to connect with each other.
Some units have multiple input/output options.
Should we use OF graph ports to tell the connections ?
"

https://lists.infradead.org/pipermail/linux-arm-kernel/2023-August/861811.html

I hope we don't end up using the graph binding, as there are too
many input/output options between processing units in the pixel engine,
e.g.,

"
Selection of the source for the sec input of the layerblend0 module
000000b - Unit layerblend0 input port sec is disabled
010100b - Unit layerblend0 input port sec is connected to output of unit fetchwarp2
010110b - Unit layerblend0 input port sec is connected to output of unit fetchdecode0
011000b - Unit layerblend0 input port sec is connected to output of unit fetchdecode1
011010b - Unit layerblend0 input port sec is connected to output of unit fetchlayer0
011011b - Unit layerblend0 input port sec is connected to output of unit matrix4
011100b - Unit layerblend0 input port sec is connected to output of unit hscaler4
011101b - Unit layerblend0 input port sec is connected to output of unit vscaler4
011110b - Unit layerblend0 input port sec is connected to output of unit matrix5
011111b - Unit layerblend0 input port sec is connected to output of unit hscaler5
100000b - Unit layerblend0 input port sec is connected to output of unit vscaler5

Selection of the source for the prim input of the layerblend0 module
000000b - Unit layerblend0 input port prim is disabled
000000b - Unit layerblend0 input port prim is connected to output of unit constframe1
001010b - Unit layerblend0 input port prim is connected to output of unit blitblend9
001100b - Unit layerblend0 input port prim is connected to output of unit constframe0
001110b - Unit layerblend0 input port prim is connected to output of unit constframe4
010010b - Unit layerblend0 input port prim is connected to output of unit constframe5
011011b - Unit layerblend0 input port prim is connected to output of unit matrix4
011100b - Unit layerblend0 input port prim is connected to output of unit hscaler4
011101b - Unit layerblend0 input port prim is connected to output of unit vscaler4
011110b - Unit layerblend0 input port prim is connected to output of unit matrix5
011111b - Unit layerblend0 input port prim is connected to output of unit hscaler5
100000b - Unit layerblend0 input port prim is connected to output of unit vscaler5
"

Also, Matrix, GammarCor and Dither in the display engine can be bypassed.
Matrix can be put at optional position(1 or 2).  Signature can be tapped
after FrameGen, GammaCor, Matrix or Dither.

FrameGen -> Matrix(1) -> GammaCor -> Maxtrix(2) -> Dither -> TCon

Aside from the alias approach, another idea is to specify the instance
number in compatible string, like "fsl,imx8qxp-dc-constframe5", no?

> 
> Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
new file mode 100644
index 000000000000..80f826289309
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-constframe.yaml
@@ -0,0 +1,51 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-constframe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Constant Frame
+
+description: |
+  The Constant Frame unit is used instead of a Fetch unit where generation of
+  constant color frames only is sufficient. This is the case for the background
+  planes of content and safety streams in a Display Controller.
+
+  The color can be setup to any RGBA value.
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-constframe
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pec
+      - const: cfg
+
+  fsl,dc-cf-id:
+    description: Constant Frame unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 4, 5]
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - fsl,dc-cf-id
+
+additionalProperties: false
+
+examples:
+  - |
+    constframe@56180960 {
+        compatible = "fsl,imx8qxp-dc-constframe";
+        reg = <0x56180960 0x3>, <0x56184400 0x400>;
+        reg-names = "pec", "cfg";
+        fsl,dc-cf-id = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
new file mode 100644
index 000000000000..45957db3aadf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-extdst.yaml
@@ -0,0 +1,79 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller External Destination Interface
+
+description: |
+  The External Destination unit is the interface between the internal pixel
+  processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha,
+  and a Display Engine.
+
+  It comprises the following built-in Gamma apply function.
+
+  +------X-----------------------+
+  |      |          ExtDst Unit  |
+  |      V                       |
+  |  +-------+                   |
+  |  | Gamma |                   |
+  |  +-------+                   |
+  |      |                       |
+  |      V                       +
+  +------X-----------------------+
+
+  The output format is 24-bit RGB plus 1-bit Alpha. Conversion from 10 to 8
+  bits is done by LSBit truncation.  Alpha output bit is 1 for input 255, 0
+  otherwise.
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-extdst
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pec
+      - const: cfg
+
+  interrupts:
+    maxItems: 3
+
+  interrupt-names:
+    items:
+      - const: shdload
+      - const: framecomplete
+      - const: seqcomplete
+
+  fsl,dc-ed-id:
+    description: External Destination unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 4, 5]
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - fsl,dc-ed-id
+
+additionalProperties: false
+
+examples:
+  - |
+    extdst@56180980 {
+        compatible = "fsl,imx8qxp-dc-extdst";
+        reg = <0x56180980 0x7>, <0x56184800 0x400>;
+        reg-names = "pec", "cfg";
+        interrupt-parent = <&dc0_intc>;
+        interrupts = <3>, <4>, <5>;
+        interrupt-names = "shdload", "framecomplete", "seqcomplete";
+        fsl,dc-ed-id = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
new file mode 100644
index 000000000000..d459573828ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml
@@ -0,0 +1,37 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchlayer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Fetchlayer
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+allOf:
+  - $ref: fsl,imx8qxp-dc-fetchunit-common.yaml#
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-fetchlayer
+
+  fsl,dc-fl-id:
+    description: Fetchlayer unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    const: 0
+
+required:
+  - compatible
+  - fsl,dc-fl-id
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    fetchlayer@56180ac0 {
+        compatible = "fsl,imx8qxp-dc-fetchlayer";
+        reg = <0x56180ac0 0x3>, <0x56188400 0x800>;
+        reg-names = "pec", "cfg";
+        fsl,dc-fl-id = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
new file mode 100644
index 000000000000..a7a568672dc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml
@@ -0,0 +1,125 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchunit-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Fetch Unit
+
+description: |
+  The Fetch Unit is the interface between the AXI bus for source buffer access
+  and the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit
+  Alpha.
+
+  It is used to generate foreground planes in Display Controllers and source
+  planes in Blit Engines, and comprises the following built-in functions to
+  convert a wide range of frame buffer types.
+
+  +---------X-----------------------------------------+
+  |         |                           Fetch Unit    |
+  |         V                                         |
+  |    +---------+                                    |
+  |    |         |                                    |
+  |    | Decode  | Decompression [Decode]             |
+  |    |         |                                    |
+  |    +---------+                                    |
+  |         |                                         |
+  |         V                                         |
+  |    +---------+                                    |
+  |    | Clip &  | Clip Window [All]                  |
+  |    | Overlay | Plane composition [Layer, Warp]    |
+  |    |         |                                    |
+  |    +---------+                                    |
+  |         |                                         |
+  |         V                                         |
+  |    +---------+                                    |
+  |    | Re-     | Flip/Rotate/Repl./Drop [All]       |
+  X--> | sample  | Perspective/Affine warping [Persp] |
+  | |  |         | Arbitrary warping [Warp, Persp]    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  |         |                                    |
+  | |  | Palette | Color Palette [Layer, Decode]      |
+  | |  |         |                                    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  | Extract | Raw to RGBA/YUV [All]              |
+  | |  | &       | Bit width expansion [All]          |
+  | |  | Expand  |                                    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  |         | Planar to packed                   |
+  | |->| Combine | [Decode, Warp, Persp]              |
+  | |  |         |                                    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  |         | YUV422 to YUV444                   |
+  | |  | Chroma  | [Decode, Persp]                    |
+  | |  |         |                                    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  |         | YUV to RGB                         |
+  | |  | Color   | [Warp, Persp, Decode, Layer]       |
+  | |  |         |                                    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  |         | Gamma removal                      |
+  | |  | Gamma   | [Warp, Persp, Decode, Layer]       |
+  | |  |         |                                    |
+  | |  +---------+                                    |
+  | |       |                                         |
+  | |       V                                         |
+  | |  +---------+                                    |
+  | |  |         | Alpla multiply, RGB pre-multiply   |
+  |  ->| Multiply| [Warp, Persp, Decode, Layer]       |
+  |    |         |                                    |
+  |     ---------                                     |
+  |         |                                         |
+  |         V                                         |
+  |    +---------+                                    |
+  |    |         | Bilinear filter                    |
+  |    | Filter  | [Warp, Persp]                      |
+  |    |         |                                    |
+  |    +---------+                                    |
+  |         |                                         |
+  |         V                                         |
+  +---------X-----------------------------------------+
+
+  Note that different derivatives of the Fetch Unit exist. Each implements a
+  specific subset only of the pipeline stages shown above. Restrictions for the
+  units are specified in [square brackets].
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pec
+      - const: cfg
+
+  fsl,prg:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Optional Prefetch Resolve Gasket associated with the Fetch Unit.
+
+required:
+  - reg
+  - reg-names
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
new file mode 100644
index 000000000000..5613f84e6112
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml
@@ -0,0 +1,37 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchwarp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Fetchwarp
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+allOf:
+  - $ref: fsl,imx8qxp-dc-fetchunit-common.yaml#
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-fetchwarp
+
+  fsl,dc-fw-id:
+    description: Fetchwarp unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [2, 9]
+
+required:
+  - compatible
+  - fsl,dc-fw-id
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    fetchwarp@56180a60 {
+        compatible = "fsl,imx8qxp-dc-fetchwarp";
+        reg = <0x56180a60 0x4>, <0x56186400 0x400>;
+        reg-names = "pec", "cfg";
+        fsl,dc-fw-id = <2>;
+    };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
new file mode 100644
index 000000000000..3fe666f35a1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-framegen.yaml
@@ -0,0 +1,71 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-framegen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Frame Generator
+
+description:
+  The Frame Generator (FrameGen) module generates a programmable video timing
+  and optionally allows to synchronize the generated video timing to external
+  synchronization signals.
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-framegen
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 8
+
+  interrupt-names:
+    items:
+      - const: int0
+      - const: int1
+      - const: int2
+      - const: int3
+      - const: primsync_on
+      - const: primsync_off
+      - const: secsync_on
+      - const: secsync_off
+
+  fsl,dc-fg-id:
+    description: Frame Generator unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - fsl,dc-fg-id
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8-lpcg.h>
+    #include <dt-bindings/firmware/imx/rsrc.h>
+
+    framegen@5618b800 {
+        compatible = "fsl,imx8qxp-dc-framegen";
+        reg = <0x5618b800 0x400>;
+        clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>;
+        interrupt-parent = <&dc0_intc>;
+        interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>;
+        interrupt-names = "int0", "int1", "int2", "int3",
+                          "primsync_on", "primsync_off",
+                          "secsync_on", "secsync_off";
+        fsl,dc-fg-id = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
new file mode 100644
index 000000000000..7da26d5859d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-layerblend.yaml
@@ -0,0 +1,46 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-layerblend.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Layer Blend Unit
+
+description: Combines two input frames to a single output frame.
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-layerblend
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: pec
+      - const: cfg
+
+  fsl,dc-lb-id:
+    description: Layer Blend unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3]
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - fsl,dc-lb-id
+
+additionalProperties: false
+
+examples:
+  - |
+    layerblend@56180ba0 {
+        compatible = "fsl,imx8qxp-dc-layerblend";
+        reg = <0x56180ba0 0x4>, <0x5618a400 0x400>;
+        reg-names = "pec", "cfg";
+        fsl,dc-lb-id = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
new file mode 100644
index 000000000000..32a57de1038d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-tcon.yaml
@@ -0,0 +1,41 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-tcon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Timing Controller
+
+description:
+  The TCon can generate a wide range of customized synchronization signals and
+  does the mapping of the color bits to the output.
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-tcon
+
+  reg:
+    maxItems: 1
+
+  fsl,dc-tc-id:
+    description: Timing Controller unit instance number
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+
+required:
+  - compatible
+  - reg
+  - fsl,dc-tc-id
+
+additionalProperties: false
+
+examples:
+  - |
+    tcon@5618c800 {
+        compatible = "fsl,imx8qxp-dc-tcon";
+        reg = <0x5618c800 0x800>;
+        fsl,dc-tc-id = <0>;
+    };