| Message ID | 20240717-alpha-blending-v4-4-4b1c806c0749@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support alpha blending in MTK display driver | expand |
Hi, Shawn: On Wed, 2024-07-17 at 13:24 +0800, Hsiao Chien Sung via B4 Relay wrote: > > External email : Please do not click links or open attachments until you have verified the sender or the content. > From: Hsiao Chien Sung <shawn.sung@mediatek.com> > > Support "Pre-multiplied" alpha blending mode in Mixer. > Before this patch, only the coverage mode is supported. > > To replace the default setting that is set in mtk_ethdr_config(), > we change mtk_ddp_write_mask() to mtk_ddp_write(), and this change will > also reset the NON_PREMULTI_SOURCE bit that was assigned in > mtk_ethdr_config(). Therefore, we must still set NON_PREMULTI_SOURCE bit > if the blend mode is not DRM_MODE_BLEND_PREMULTI. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_ethdr.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c > index 80ccdad3741b..d1d9cf8b10e1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c > @@ -36,6 +36,7 @@ > #define MIX_SRC_L0_ENBIT(0) > #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n)) > #define NON_PREMULTI_SOURCE(2 << 12) > +#define PREMULTI_SOURCE(3 << 12) > #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n)) > #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n)) > #define MIX_FUNC_DCM00x120 > @@ -176,6 +177,11 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, > alpha_con |= state->base.alpha & MIXER_ALPHA; > } > > +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) > +alpha_con |= PREMULTI_SOURCE; > +else > +alpha_con |= NON_PREMULTI_SOURCE; > + > if ((state->base.fb && !state->base.fb->format->has_alpha) || > state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) { > /* > @@ -193,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, > mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, > mixer->regs, MIX_L_SRC_SIZE(idx)); > mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); > -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), > - 0x1ff); > +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); > mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, > BIT(idx)); > } > > -- > 2.43.0 > >
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 80ccdad3741b..d1d9cf8b10e1 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -36,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -176,6 +177,11 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, alpha_con |= state->base.alpha & MIXER_ALPHA; } + if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) + alpha_con |= PREMULTI_SOURCE; + else + alpha_con |= NON_PREMULTI_SOURCE; + if ((state->base.fb && !state->base.fb->format->has_alpha) || state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) { /* @@ -193,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), - 0x1ff); + mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, BIT(idx)); }