| Message ID | 20240725205109.209743-2-hamza.mahfooz@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/vblank: add dynamic per-crtc vblank configuration support | expand |
On Thu, Jul 25, 2024 at 04:51:09PM -0400, Hamza Mahfooz wrote: > Hook up drm_crtc_vblank_on_config() in amdgpu_dm. So, that we can enable > PSR and other static screen optimizations more quickly, while avoiding > stuttering issues that are accompanied by the following dmesg error: > > [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 > > This also allows us to mimic how vblanking is handled by the windows > amdgpu driver. > > Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 49 +++++++++++++++++-- > 1 file changed, 44 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 07e373deb814..780e31a2d456 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -7952,7 +7952,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, > > static void manage_dm_interrupts(struct amdgpu_device *adev, > struct amdgpu_crtc *acrtc, > - bool enable) > + struct dm_crtc_state *acrtc_state) > { > /* > * We have no guarantee that the frontend index maps to the same > @@ -7964,9 +7964,47 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, > amdgpu_display_crtc_idx_to_irq_type( > adev, > acrtc->crtc_id); > + struct dc_crtc_timing *timing; > + int vsync_rate_hz; > + int offdelay = 30; > + > + if (acrtc_state) { > + timing = &acrtc_state->stream->timing; > + > + vsync_rate_hz = div64_u64(div64_u64((timing->pix_clk_100hz * > + (uint64_t)100), > + timing->v_total), > + timing->h_total); > + > + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= > + IP_VERSION(3, 5, 0) && (adev->flags & AMD_IS_APU)) { > + if (vsync_rate_hz) > + /* at least 2 frames */ > + offdelay = 2000 / vsync_rate_hz + 1; > + > + if (acrtc_state->stream->link->psr_settings.psr_version < > + DC_PSR_VERSION_UNSUPPORTED) { > + const struct drm_vblank_crtc_config config = { > + .offdelay_ms = offdelay, > + .disable_immediate = false > + }; > + > + drm_crtc_vblank_on_config(&acrtc->base, > + &config); > + } else { > + const struct drm_vblank_crtc_config config = { > + .offdelay_ms = 0, > + .disable_immediate = true Uh, I think it'd be better to use drm_crtc_vblank_on() here and then have a 2nd patch which re-enables the immediate vblank disabling and references the right revert for context. Plus this feels like a demidlayer hack, but I don't understand enough DC code to know a better place ... -Sima > + }; > + > + drm_crtc_vblank_on_config(&acrtc->base, > + &config); > + } > + > + } else { > + drm_crtc_vblank_on(&acrtc->base); > + } > > - if (enable) { > - drm_crtc_vblank_on(&acrtc->base); > amdgpu_irq_get( > adev, > &adev->pageflip_irq, > @@ -8947,7 +8985,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, > if (old_crtc_state->active && > (!new_crtc_state->active || > drm_atomic_crtc_needs_modeset(new_crtc_state))) { > - manage_dm_interrupts(adev, acrtc, false); > + manage_dm_interrupts(adev, acrtc, NULL); > dc_stream_release(dm_old_crtc_state->stream); > } > } > @@ -9465,7 +9503,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) > drm_atomic_crtc_needs_modeset(new_crtc_state))) { > dc_stream_retain(dm_new_crtc_state->stream); > acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; > - manage_dm_interrupts(adev, acrtc, true); > + manage_dm_interrupts(adev, acrtc, > + to_dm_crtc_state(new_crtc_state)); > } > /* Handle vrr on->off / off->on transitions */ > amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); > -- > 2.45.2 >
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 07e373deb814..780e31a2d456 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7952,7 +7952,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - bool enable) + struct dm_crtc_state *acrtc_state) { /* * We have no guarantee that the frontend index maps to the same @@ -7964,9 +7964,47 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, amdgpu_display_crtc_idx_to_irq_type( adev, acrtc->crtc_id); + struct dc_crtc_timing *timing; + int vsync_rate_hz; + int offdelay = 30; + + if (acrtc_state) { + timing = &acrtc_state->stream->timing; + + vsync_rate_hz = div64_u64(div64_u64((timing->pix_clk_100hz * + (uint64_t)100), + timing->v_total), + timing->h_total); + + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= + IP_VERSION(3, 5, 0) && (adev->flags & AMD_IS_APU)) { + if (vsync_rate_hz) + /* at least 2 frames */ + offdelay = 2000 / vsync_rate_hz + 1; + + if (acrtc_state->stream->link->psr_settings.psr_version < + DC_PSR_VERSION_UNSUPPORTED) { + const struct drm_vblank_crtc_config config = { + .offdelay_ms = offdelay, + .disable_immediate = false + }; + + drm_crtc_vblank_on_config(&acrtc->base, + &config); + } else { + const struct drm_vblank_crtc_config config = { + .offdelay_ms = 0, + .disable_immediate = true + }; + + drm_crtc_vblank_on_config(&acrtc->base, + &config); + } + + } else { + drm_crtc_vblank_on(&acrtc->base); + } - if (enable) { - drm_crtc_vblank_on(&acrtc->base); amdgpu_irq_get( adev, &adev->pageflip_irq, @@ -8947,7 +8985,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, if (old_crtc_state->active && (!new_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))) { - manage_dm_interrupts(adev, acrtc, false); + manage_dm_interrupts(adev, acrtc, NULL); dc_stream_release(dm_old_crtc_state->stream); } } @@ -9465,7 +9503,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_crtc_needs_modeset(new_crtc_state))) { dc_stream_retain(dm_new_crtc_state->stream); acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; - manage_dm_interrupts(adev, acrtc, true); + manage_dm_interrupts(adev, acrtc, + to_dm_crtc_state(new_crtc_state)); } /* Handle vrr on->off / off->on transitions */ amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
Hook up drm_crtc_vblank_on_config() in amdgpu_dm. So, that we can enable PSR and other static screen optimizations more quickly, while avoiding stuttering issues that are accompanied by the following dmesg error: [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 This also allows us to mimic how vblanking is handled by the windows amdgpu driver. Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 49 +++++++++++++++++-- 1 file changed, 44 insertions(+), 5 deletions(-)