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[68.4.168.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fed7ee4ce6sm112339595ad.157.2024.07.30.22.54.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jul 2024 22:54:54 -0700 (PDT) From: Remington Brasga To: Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xinhui Pan , David Airlie , Daniel Vetter Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, Remington Brasga Subject: [PATCH] drm/amdgpu/uvd4: fix mask and shift definitions Date: Wed, 31 Jul 2024 05:54:51 +0000 Message-Id: <20240731055451.15467-1-rbrasga@uci.edu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 31 Jul 2024 07:19:04 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" A few define's are listed twice with different, incorrect values. This fix sets them appropriately. Signed-off-by: Remington Brasga --- The second UVD_LMI_CTRL__RFU_MASK is incorrect, so it was removed. It should be `0xf800 0000`. The first UVD_LMI_CTRL__RFU__SHIFT is incorrect, so it was removed. It should bei `0x1a`. This change aligns the uvd definitions, please refer to: drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h index 8ee3149df5b7..2ef1273e65ab 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h @@ -340,8 +340,6 @@ #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x00000009 #define UVD_LMI_CTRL__RFU_MASK 0xf8000000L -#define UVD_LMI_CTRL__RFU_MASK 0xfc000000L -#define UVD_LMI_CTRL__RFU__SHIFT 0x0000001a #define UVD_LMI_CTRL__RFU__SHIFT 0x0000001b #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015