From patchwork Wed Aug 7 11:07:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13756162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9719CC52D6F for ; Wed, 7 Aug 2024 11:23:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D19B10E4BB; Wed, 7 Aug 2024 11:23:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=collabora.com header.i=cristian.ciocaltea@collabora.com header.b="UNt/LIzW"; dkim-atps=neutral Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7053810E4C3 for ; Wed, 7 Aug 2024 11:23:19 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; t=1723028890; cv=none; d=zohomail.com; s=zohoarc; b=DSaHmL4WZLy9+PvCJPcG5p9s0MQXivCdH5mSexomRgv7t9dY24fosMRvMb09wr+L18/wUJNseKtnl55N7Xe5oOkmfoxOoXP1JYX04uNe3IEodaWeOY1Ly1OSKIdAS0YQZWbAFuXkpmlpVLVkniciwvdNGklT6KN/91f9saHXmkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1723028890; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=mR40Azjzt4knTLDXSxrvtusTqVgpGbT68iN2X8UKRmk=; b=nZGK3W4fjhIBHkpX6TnfdZxIcqGTCaqMpVU+UHNt7XsCQyQiY/CMfRL6lspIAt1EJE1F5WAZtm6qmvgliIFhQ0jSgu2mF0BuR/cg91yyJcDvGZc/N3fqy54qv0PGZces8wKg0kilhhR0/qI2GI6mYjWtQ12VEJUeazsfhn0ZEsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=cristian.ciocaltea@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1723028890; s=zohomail; d=collabora.com; i=cristian.ciocaltea@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=mR40Azjzt4knTLDXSxrvtusTqVgpGbT68iN2X8UKRmk=; b=UNt/LIzW3J7Clw3f4Nwrl7O6mRSHd/saOTwRE7CtIb7ntOOW0TUTmcvyTFaBkFrz f+CdrEFiQPWUn9c42K0sy1fHnXdOeuCIQTxNxQt5mdrHSqufHW3K546uikK5QeSvNJx aShjHesPVwMArgGo5YuezAFja01Z6Bt/Pm3tbl8M= Received: by mx.zohomail.com with SMTPS id 1723028888640197.67334448085865; Wed, 7 Aug 2024 04:08:08 -0700 (PDT) From: Cristian Ciocaltea Date: Wed, 07 Aug 2024 14:07:25 +0300 Subject: [PATCH v3 3/5] dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller MIME-Version: 1.0 Message-Id: <20240807-b4-rk3588-bridge-upstream-v3-3-60d6bab0dc7c@collabora.com> References: <20240807-b4-rk3588-bridge-upstream-v3-0-60d6bab0dc7c@collabora.com> In-Reply-To: <20240807-b4-rk3588-bridge-upstream-v3-0-60d6bab0dc7c@collabora.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Yao , Sascha Hauer Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com, Alexandre ARNOUD , Luis de Arquer X-Mailer: b4 0.14.1 X-ZohoMailClient: External X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller IP. Since this is a new IP block, quite different from those used in the previous generations of Rockchip SoCs, add a dedicated binding file. Signed-off-by: Cristian Ciocaltea --- .../display/rockchip/rockchip,dw-hdmi-qp.yaml | 188 +++++++++++++++++++++ 1 file changed, 188 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml new file mode 100644 index 000000000000..33572c88a589 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi-qp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DW HDMI QP TX Encoder + +maintainers: + - Cristian Ciocaltea + +description: + Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller + IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block. + +allOf: + - $ref: ../bridge/synopsys,dw-hdmi-qp.yaml# + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3588-dw-hdmi-qp + + clocks: + minItems: 4 + items: + - {} + - {} + - {} + - {} + # The next clocks are optional, but shall be specified in this + # order when present. + - description: TMDS/FRL link clock + - description: Video datapath clock + + clock-names: + minItems: 4 + items: + - {} + - {} + - {} + - {} + - enum: [hdp, hclk_vo1] + - const: hclk_vo1 + + interrupts: + items: + - {} + - {} + - {} + - {} + - description: HPD interrupt + + interrupt-names: + items: + - {} + - {} + - {} + - {} + - const: hpd + + phys: + maxItems: 1 + description: The HDMI/eDP PHY. + + phy-names: + const: hdmi + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to a vop node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to a hdmi-connector node. + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + items: + - const: ref + - const: hdp + + "#sound-dai-cells": + const: 0 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Most HDMI QP related data is accessed through SYS GRF regs. + + rockchip,vo1_grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Additional HDMI QP related data is accessed through VO1 GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phys + - phy-names + - ports + - resets + - reset-names + - rockchip,grf + - rockchip,vo1_grf + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfde80000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru CLK_HDMIHDP0>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = , + , + , + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy_hdmi0>; + phy-names = "hdmi"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; + }; + + port@1 { + reg = <1>; + + hdmi0_out_con0: endpoint { + remote-endpoint = <&hdmi_con0_in>; + }; + }; + }; + }; + };