diff mbox series

[v3,4/4] drm/msm: Fix UBWC macrotile_mode for a680

Message ID 20240807-msm-tiling-config-v3-4-ef1bc26efb4c@gmail.com (mailing list archive)
State New, archived
Headers show
Series drm/msm: Further expose UBWC tiling parameters | expand

Commit Message

Connor Abbott Aug. 7, 2024, 1:04 p.m. UTC 
Make it match the MDSS settings for sc8180x and downstream.

Note that without the previous commit that exposes the value of
macrotile_mode to mesa, this will break mesa which expects the legacy
default value of 0. Therefore we do *not* want to backport it.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7c2fdd1e7684..7ceca633ceea 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -519,6 +519,9 @@  static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
 	if (adreno_is_a640_family(gpu))
 		gpu->ubwc_config.amsbc = 1;
 
+	if (adreno_is_a680(gpu))
+		gpu->ubwc_config.macrotile_mode = 1;
+
 	if (adreno_is_a650(gpu) ||
 	    adreno_is_a660(gpu) ||
 	    adreno_is_a690(gpu) ||