@@ -4,35 +4,87 @@
*/
#include "i915_drv.h"
-#include "intel_gt.h"
#include "intel_gt_ccs_mode.h"
#include "intel_gt_regs.h"
static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
{
+ unsigned long cslices_mask = gt->ccs.cslices;
+ u32 mode_val = 0;
+ /* CCS mode, i.e. number of CCS engines to be enabled */
+ u32 width = 1;
+ /* CCS engine id, i.e. the engines position in the engine's bitmask */
+ int engine;
int cslice;
- u32 mode = 0;
- int first_ccs = __ffs(CCS_MASK(gt));
- /* Build the value for the fixed CCS load balancing */
+ /*
+ * The mode has two bit dedicated for each engine
+ * that will be used for the CCS balancing algorithm:
+ *
+ * BIT | CCS slice
+ * ------------------
+ * 0 | CCS slice
+ * 1 | 0
+ * ------------------
+ * 2 | CCS slice
+ * 3 | 1
+ * ------------------
+ * 4 | CCS slice
+ * 5 | 2
+ * ------------------
+ * 6 | CCS slice
+ * 7 | 3
+ * ------------------
+ *
+ * When a CCS slice is not available, then we will write 0x7,
+ * oterwise we will write the user engine id which load will
+ * be forwarded to that slice.
+ *
+ * The possible configurations are:
+ *
+ * 1 engine (ccs0):
+ * slice 0, 1, 2, 3: ccs0
+ *
+ * 2 engines (ccs0, ccs1):
+ * slice 0, 2: ccs0
+ * slice 1, 3: ccs1
+ *
+ * 4 engines (ccs0, ccs1, ccs2, ccs3):
+ * slice 0: ccs0
+ * slice 1: ccs1
+ * slice 2: ccs2
+ * slice 3: ccs3
+ */
+ engine = __ffs(cslices_mask);
+
for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
- if (gt->ccs.cslices & BIT(cslice))
+ if (!(cslices_mask & BIT(cslice))) {
/*
- * If available, assign the cslice
- * to the first available engine...
+ * If not available, mark the slice as unavailable
+ * and no task will be dispatched here.
*/
- mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
+ mode_val |= XEHP_CCS_MODE_CSLICE(cslice,
+ XEHP_CCS_MODE_CSLICE_MASK);
+ continue;
+ }
+
+ mode_val |= XEHP_CCS_MODE_CSLICE(cslice, engine);
- else
+ if (!width) {
/*
- * ... otherwise, mark the cslice as
- * unavailable if no CCS dispatches here
+ * CCS mode, will be used later to
+ * reset to a flexible value
*/
- mode |= XEHP_CCS_MODE_CSLICE(cslice,
- XEHP_CCS_MODE_CSLICE_MASK);
+ width = 1;
+ engine = __ffs(cslices_mask);
+ continue;
+ }
+
+ width--;
+ engine = find_next_bit(&cslices_mask, I915_MAX_CCS, engine + 1);
}
- gt->ccs.mode_reg_val = mode;
+ gt->ccs.mode_reg_val = mode_val;
}
void intel_gt_ccs_mode_init(struct intel_gt *gt)
@@ -6,7 +6,7 @@
#ifndef __INTEL_GT_CCS_MODE_H__
#define __INTEL_GT_CCS_MODE_H__
-struct intel_gt;
+#include "intel_gt.h"
void intel_gt_ccs_mode_init(struct intel_gt *gt);
Until now, we have only set CCS mode balancing to 1, which means that only one compute engine is exposed to the user. The stream of compute commands submitted to that engine is then shared among all the dedicated execution units. This is done by calling the 'intel_gt_apply_ccs_mode(); function. With this change, the aforementioned function takes an additional parameter called 'mode' that specifies the desired mode to be set for the CCS engines balancing. The mode parameter can have the following values: - mode = 0: CCS load balancing mode 1 (1 CCS engine exposed) - mode = 1: CCS load balancing mode 2 (2 CCS engines exposed) - mode = 3: CCS load balancing mode 4 (4 CCS engines exposed) This allows us to generate the appropriate register value to be written to CCS_MODE, configuring how the exposed engine streams will be submitted to the execution units. No functional changes are intended yet, as no mode higher than '0' is currently being set. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 80 +++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- 2 files changed, 67 insertions(+), 15 deletions(-)