| Message ID | 20240822064650.1473930-4-rohiagar@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Devicetree updates for MT8186 | expand |
On Thu, Aug 22, 2024 at 06:46:50AM +0000, Rohit Agarwal wrote: > Add clock/irq/efuse setting in svs nodes for mt8186 SoC. > > Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index e27c69ec8bdd..a51f3d8ce745 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -1361,6 +1361,18 @@ spi0: spi@1100a000 { > status = "disabled"; > }; > > + svs: svs@1100b000 { There's already another node at address 1100b000: lvts: thermal-sensor@1100b000 You should set the starting address of the SVS to 1100bc00 and decrease the iospace for lvts to avoid intersection. See this commit for a similar change on mt8195: https://lore.kernel.org/all/20231121125044.78642-21-angelogioacchino.delregno@collabora.com/ Thanks, Nícolas
On 22/08/24 9:36 PM, Nícolas F. R. A. Prado wrote: > On Thu, Aug 22, 2024 at 06:46:50AM +0000, Rohit Agarwal wrote: >> Add clock/irq/efuse setting in svs nodes for mt8186 SoC. >> >> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> >> --- >> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >> index e27c69ec8bdd..a51f3d8ce745 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >> @@ -1361,6 +1361,18 @@ spi0: spi@1100a000 { >> status = "disabled"; >> }; >> >> + svs: svs@1100b000 { > There's already another node at address 1100b000: > > lvts: thermal-sensor@1100b000 > > You should set the starting address of the SVS to 1100bc00 and decrease the > iospace for lvts to avoid intersection. See this commit for a similar change on > mt8195: > https://lore.kernel.org/all/20231121125044.78642-21-angelogioacchino.delregno@collabora.com/ Sure. Will update this according to the reference. Thanks, Rohit.
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index e27c69ec8bdd..a51f3d8ce745 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1361,6 +1361,18 @@ spi0: spi@1100a000 { status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8186-svs"; + reg = <0 0x1100b000 0 0x400>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&lvts_e_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>; + reset-names = "svs_rst"; + }; + pwm0: pwm@1100e000 { compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1676,6 +1688,14 @@ efuse: efuse@11cb0000 { #address-cells = <1>; #size-cells = <1>; + lvts_e_data1: data@1cc { + reg = <0x1cc 0x14>; + }; + + svs_calibration: calib@550 { + reg = <0x550 0x50>; + }; + gpu_speedbin: gpu-speedbin@59c { reg = <0x59c 0x4>; bits = <0 3>;
Add clock/irq/efuse setting in svs nodes for mt8186 SoC. Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)