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[174.20.195.90]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4ced2eaa1e7sm778553173.132.2024.08.30.08.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 08:29:22 -0700 (PDT) From: Shimrra Shai To: shimrrashai@gmail.com Cc: Laurent.pinchart@ideasonboard.com, aarnoud@me.com, airlied@gmail.com, algea.cao@rock-chips.com, andrzej.hajda@intel.com, andy.yan@rock-chips.com, conor+dt@kernel.org, cristian.ciocaltea@collabora.com, daniel@ffwll.ch, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, heiko@sntech.de, hjc@rock-chips.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, krzk+dt@kernel.org, ldearquer@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, maarten.lankhorst@linux.intel.com, markyao0591@gmail.com, mripard@kernel.org, neil.armstrong@linaro.org, rfoss@kernel.org, robh@kernel.org, s.hauer@pengutronix.de, tzimmermann@suse.de Subject: [PATCH v5? 6/6] dts: rockchip: add HDMI0 entry for RK3588 and change VO0/1 GRF compatibles Date: Fri, 30 Aug 2024 10:29:12 -0500 Message-ID: <20240830152912.9092-1-shimrrashai@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240830152132.8894-1-shimrrashai@gmail.com> References: <20240830152132.8894-1-shimrrashai@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 30 Aug 2024 22:08:56 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index b6e4df180..76cb0f7f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -582,13 +582,13 @@ vop_grf: syscon@fd5a4000 { }; vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; + compatible = "rockchip,rk3588-vo0-grf", "syscon"; reg = <0x0 0xfd5a6000 0x0 0x2000>; clocks = <&cru PCLK_VO0GRF>; }; vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; + compatible = "rockchip,rk3588-vo1-grf", "syscon"; reg = <0x0 0xfd5a8000 0x0 0x100>; clocks = <&cru PCLK_VO1GRF>; }; @@ -1254,6 +1254,46 @@ i2s9_8ch: i2s@fddfc000 { status = "disabled"; }; + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfde80000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru CLK_HDMIHDP0>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = , + , + , + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy_hdmi0>; + phy-names = "hdmi"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo1-grf = <&vo1_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in: port@0 { + reg = <0>; + }; + + hdmi0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>;