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([2405:201:d007:50c2:4888:86b4:6f32:9ae]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2dab6e5dc04sm1466452a91.1.2024.09.06.10.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 10:46:09 -0700 (PDT) From: Vamsi Krishna Brahmajosyula To: dri-devel@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, rodrigo.vivi@intel.com, joonas.lahtinen@linux.intel.com, tursulin@ursulin.net, airlied@gmail.com, daniel@ffwll.ch, skhan@linuxfoundation.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/i915/cx0: Use one lane to set power state to ready in DP alt mode Date: Fri, 6 Sep 2024 23:16:01 +0530 Message-ID: <20240906174601.9271-1-vamsikrishna.brahmajosyula@gmail.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 06 Sep 2024 23:45:00 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In DP alt mode one lane is owned by display and the other by usb intel_cx0pll_enable currently performs a power cycle ready on both the lanes in all cases. Address the todo to perfom power state ready only on the display lane when DP alt mode is enabled. Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mode. Signed-off-by: Vamsi Krishna Brahmajosyula --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) base-commit: b831f83e40a24f07c8dcba5be408d93beedc820f diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4a6c3040ca15..47aa0418379c 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2949,9 +2949,13 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, /* * 3. Change Phy power state to Ready. - * TODO: For DP alt mode use only one lane. + * For DP alt mode use only one lane. */ - intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, + if (intel_tc_port_in_dp_alt_mode(dig_port)) + intel_cx0_powerdown_change_sequence(encoder, maxpclk_lane, + CX0_P2_STATE_READY); + else + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, CX0_P2_STATE_READY); /*