| Message ID | 20240911042738.3886250-1-yanzhen@vivo.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] drm/amdgpu: fix typo in the comment | expand |
Am 11.09.24 um 06:27 schrieb Yan Zhen: > Correctly spelled comments make it easier for the reader to understand > the code. > > Replace 'udpate' with 'update' in the comment & > replace 'recieved' with 'received' in the comment & > replace 'dsiable' with 'disable' in the comment & > replace 'Initiailize' with 'Initialize' in the comment & > replace 'disble' with 'disable' in the comment & > replace 'Disbale' with 'Disable' in the comment & > replace 'enogh' with 'enough' in the comment & > replace 'availabe' with 'available' in the comment. > > Signed-off-by: Yan Zhen <yanzhen@vivo.com> Acked-by: Christian König <christian.koenig@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2 +- > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c | 2 +- > 8 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c > index 57bda66e8..2ca127173 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c > @@ -511,7 +511,7 @@ static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *h > return -EINVAL; > } > > - /* udpate aca bank to aca source error_cache first */ > + /* update aca bank to aca source error_cache first */ > ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > index 189574d53..e9e599ff3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > @@ -2853,7 +2853,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp) > if (ret) > return ret; > > - /* Start rlc autoload after psp recieved all the gfx firmware */ > + /* Start rlc autoload after psp received all the gfx firmware */ > if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? > adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { > ret = psp_rlc_autoload_start(psp); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 61a2f386d..71069b198 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -882,7 +882,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, > if (ret) > return ret; > > - /* gfx block ras dsiable cmd must send to ras-ta */ > + /* gfx block ras disable cmd must send to ras-ta */ > if (head->block == AMDGPU_RAS_BLOCK__GFX) > con->features |= BIT(head->block); > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > index b8bc7fa8c..74adb983a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -1970,7 +1970,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) > DRM_INFO("amdgpu: %uM of GTT memory ready.\n", > (unsigned int)(gtt_size / (1024 * 1024))); > > - /* Initiailize doorbell pool on PCI BAR */ > + /* Initialize doorbell pool on PCI BAR */ > r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); > if (r) { > DRM_ERROR("Failed initializing doorbell heap.\n"); > diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c > index 6c1891889..d4f72e47a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c > @@ -153,7 +153,7 @@ static void imu_v11_0_setup(struct amdgpu_device *adev) > WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); > } > > - //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB > + //disable imu Rtavfs, SmsRepair, DfllBTC, and ClkB > imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); > imu_reg_val |= 0x10007; > WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > index fa479dfa1..739fce4fa 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > @@ -365,7 +365,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, > > data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; > } else { > - /* Disbale ASPM L1 */ > + /* Disable ASPM L1 */ > data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; > /* Disable ASPM TxL0s */ > data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > index aa637541d..e65194fe9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > @@ -710,7 +710,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) > upper_32_bits(wptr_gpu_addr)); > wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); > if (ring->use_pollmem) { > - /*wptr polling is not enogh fast, directly clean the wptr register */ > + /*wptr polling is not enough fast, directly clean the wptr register */ > WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); > wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, > SDMA0_GFX_RB_WPTR_POLL_CNTL, > diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c > index e4e30b9d4..c04fdd2d5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c > @@ -60,7 +60,7 @@ static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *f > { > u32 data; > > - /* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */ > + /* CGTT_ROM_CLK_CTRL0 is not available for APUs */ > if (adev->flags & AMD_IS_APU) > return; >
Applied. Thanks! On Wed, Sep 11, 2024 at 2:58 AM Christian König <christian.koenig@amd.com> wrote: > > Am 11.09.24 um 06:27 schrieb Yan Zhen: > > Correctly spelled comments make it easier for the reader to understand > > the code. > > > > Replace 'udpate' with 'update' in the comment & > > replace 'recieved' with 'received' in the comment & > > replace 'dsiable' with 'disable' in the comment & > > replace 'Initiailize' with 'Initialize' in the comment & > > replace 'disble' with 'disable' in the comment & > > replace 'Disbale' with 'Disable' in the comment & > > replace 'enogh' with 'enough' in the comment & > > replace 'availabe' with 'available' in the comment. > > > > Signed-off-by: Yan Zhen <yanzhen@vivo.com> > > Acked-by: Christian König <christian.koenig@amd.com> > > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- > > drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c | 2 +- > > 8 files changed, 8 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c > > index 57bda66e8..2ca127173 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c > > @@ -511,7 +511,7 @@ static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *h > > return -EINVAL; > > } > > > > - /* udpate aca bank to aca source error_cache first */ > > + /* update aca bank to aca source error_cache first */ > > ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL); > > if (ret) > > return ret; > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > > index 189574d53..e9e599ff3 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > > @@ -2853,7 +2853,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp) > > if (ret) > > return ret; > > > > - /* Start rlc autoload after psp recieved all the gfx firmware */ > > + /* Start rlc autoload after psp received all the gfx firmware */ > > if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? > > adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { > > ret = psp_rlc_autoload_start(psp); > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > > index 61a2f386d..71069b198 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > > @@ -882,7 +882,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, > > if (ret) > > return ret; > > > > - /* gfx block ras dsiable cmd must send to ras-ta */ > > + /* gfx block ras disable cmd must send to ras-ta */ > > if (head->block == AMDGPU_RAS_BLOCK__GFX) > > con->features |= BIT(head->block); > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > index b8bc7fa8c..74adb983a 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > @@ -1970,7 +1970,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) > > DRM_INFO("amdgpu: %uM of GTT memory ready.\n", > > (unsigned int)(gtt_size / (1024 * 1024))); > > > > - /* Initiailize doorbell pool on PCI BAR */ > > + /* Initialize doorbell pool on PCI BAR */ > > r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); > > if (r) { > > DRM_ERROR("Failed initializing doorbell heap.\n"); > > diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c > > index 6c1891889..d4f72e47a 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c > > @@ -153,7 +153,7 @@ static void imu_v11_0_setup(struct amdgpu_device *adev) > > WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); > > } > > > > - //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB > > + //disable imu Rtavfs, SmsRepair, DfllBTC, and ClkB > > imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); > > imu_reg_val |= 0x10007; > > WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); > > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > > index fa479dfa1..739fce4fa 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > > @@ -365,7 +365,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, > > > > data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; > > } else { > > - /* Disbale ASPM L1 */ > > + /* Disable ASPM L1 */ > > data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; > > /* Disable ASPM TxL0s */ > > data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > index aa637541d..e65194fe9 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > @@ -710,7 +710,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) > > upper_32_bits(wptr_gpu_addr)); > > wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); > > if (ring->use_pollmem) { > > - /*wptr polling is not enogh fast, directly clean the wptr register */ > > + /*wptr polling is not enough fast, directly clean the wptr register */ > > WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); > > wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, > > SDMA0_GFX_RB_WPTR_POLL_CNTL, > > diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c > > index e4e30b9d4..c04fdd2d5 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c > > @@ -60,7 +60,7 @@ static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *f > > { > > u32 data; > > > > - /* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */ > > + /* CGTT_ROM_CLK_CTRL0 is not available for APUs */ > > if (adev->flags & AMD_IS_APU) > > return; > > >
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index 57bda66e8..2ca127173 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -511,7 +511,7 @@ static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *h return -EINVAL; } - /* udpate aca bank to aca source error_cache first */ + /* update aca bank to aca source error_cache first */ ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 189574d53..e9e599ff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2853,7 +2853,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp) if (ret) return ret; - /* Start rlc autoload after psp recieved all the gfx firmware */ + /* Start rlc autoload after psp received all the gfx firmware */ if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { ret = psp_rlc_autoload_start(psp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 61a2f386d..71069b198 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -882,7 +882,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, if (ret) return ret; - /* gfx block ras dsiable cmd must send to ras-ta */ + /* gfx block ras disable cmd must send to ras-ta */ if (head->block == AMDGPU_RAS_BLOCK__GFX) con->features |= BIT(head->block); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index b8bc7fa8c..74adb983a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1970,7 +1970,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of GTT memory ready.\n", (unsigned int)(gtt_size / (1024 * 1024))); - /* Initiailize doorbell pool on PCI BAR */ + /* Initialize doorbell pool on PCI BAR */ r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); if (r) { DRM_ERROR("Failed initializing doorbell heap.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index 6c1891889..d4f72e47a 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -153,7 +153,7 @@ static void imu_v11_0_setup(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); } - //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB + //disable imu Rtavfs, SmsRepair, DfllBTC, and ClkB imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); imu_reg_val |= 0x10007; WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index fa479dfa1..739fce4fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -365,7 +365,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; } else { - /* Disbale ASPM L1 */ + /* Disable ASPM L1 */ data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; /* Disable ASPM TxL0s */ data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index aa637541d..e65194fe9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -710,7 +710,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) upper_32_bits(wptr_gpu_addr)); wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); if (ring->use_pollmem) { - /*wptr polling is not enogh fast, directly clean the wptr register */ + /*wptr polling is not enough fast, directly clean the wptr register */ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c index e4e30b9d4..c04fdd2d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c @@ -60,7 +60,7 @@ static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *f { u32 data; - /* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */ + /* CGTT_ROM_CLK_CTRL0 is not available for APUs */ if (adev->flags & AMD_IS_APU) return;
Correctly spelled comments make it easier for the reader to understand the code. Replace 'udpate' with 'update' in the comment & replace 'recieved' with 'received' in the comment & replace 'dsiable' with 'disable' in the comment & replace 'Initiailize' with 'Initialize' in the comment & replace 'disble' with 'disable' in the comment & replace 'Disbale' with 'Disable' in the comment & replace 'enogh' with 'enough' in the comment & replace 'availabe' with 'available' in the comment. Signed-off-by: Yan Zhen <yanzhen@vivo.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-)