[6.6] drm/amd/display: Fix subvp+drr logic errors

Commit Message

Murad Masimov Sept. 16, 2024, 10:53 a.m. UTC

From: Alvin Lee <[e-mail]>

commit 8a0f02b7beed7b2b768dbdf3b79960de68f460c5 upstream.

[Why]
There is some logic error where the wrong variable was used to check for
OTG_MASTER and DPP_PIPE.

[How]
Add booleans to confirm that the expected pipes were found before
validating schedulability.

Tested-by: Daniel Wheeler <[e-mail]>
Acked-by: Rodrigo Siqueira <[e-mail]>
Reviewed-by: Samson Tam <[e-mail]>
Reviewed-by: Chaitanya Dhere <[e-mail]>
Signed-off-by: Alvin Lee <[e-mail]>
Signed-off-by: Alex Deucher <[e-mail]>
Signed-off-by: Murad Masimov <[e-mail]>
---
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c    | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

Patch

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 3d82cbef1274..7160380d5690 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -879,6 +879,8 @@  static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 	int16_t stretched_drr_us = 0;
 	int16_t drr_stretched_vblank_us = 0;
 	int16_t max_vblank_mallregion = 0;
+	bool subvp_found = false;
+	bool drr_found = false;
 
 	// Find SubVP pipe
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -891,8 +893,10 @@  static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 			continue;
 
 		// Find the SubVP pipe
-		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+			subvp_found = true;
 			break;
+		}
 	}
 
 	// Find the DRR pipe
@@ -900,15 +904,20 @@  static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 		drr_pipe = &context->res_ctx.pipe_ctx[i];
 
 		// We check for master pipe only
-		if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
-				!resource_is_pipe_type(pipe, DPP_PIPE))
+		if (!resource_is_pipe_type(drr_pipe, OTG_MASTER) ||
+				!resource_is_pipe_type(drr_pipe, DPP_PIPE))
 			continue;
 
 		if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
-				(drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
+				(drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable)) {
+			drr_found = true;
 			break;
+		}
 	}
 
+	if (!subvp_found || !drr_found)
+		return false;
+
 	main_timing = &pipe->stream->timing;
 	phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 	drr_timing = &drr_pipe->stream->timing;