| Message ID | 20240924-concurrent-wb-v2-13-7849f900e863@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ | expand |
On Tue, Sep 24, 2024 at 03:59:29PM GMT, Jessica Zhang wrote: > Add the cwb_enabled flag to msm_display topology and adjust the toplogy > to account for concurrent writeback > > Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++++++++-- > drivers/gpu/drm/msm/msm_drv.h | 2 ++ > 3 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index d53e986eee54..a7850bf844db 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -1176,6 +1176,8 @@ static struct msm_display_topology dpu_crtc_get_topology( > dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, > &crtc_state->adjusted_mode); > > + topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); > + > /* > * Datapath topology selection > * > @@ -1189,9 +1191,9 @@ static struct msm_display_topology dpu_crtc_get_topology( > * Add dspps to the reservation requirements if ctm is requested > */ > > - if (topology.num_intf == 2) > + if (topology.num_intf == 2 && !topology.cwb_enabled) > topology.num_lm = 2; > - else if (topology.num_dsc == 2) > + else if (topology.num_dsc == 2 && !topology.cwb_enabled) Is it a temporal restriction or is it a hardware limitation? Can we use two LMs with a single WB? > topology.num_lm = 2; > else if (dpu_kms->catalog->caps->has_3d_merge) > topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > index 96c80cf9f6ad..04df3056d75a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > @@ -371,8 +371,14 @@ static int _dpu_rm_reserve_ctls( > int i = 0, j, num_ctls; > bool needs_split_display; > > - /* each hw_intf needs its own hw_ctrl to program its control path */ > - num_ctls = top->num_intf; > + /* > + * For non-CWB mode, each hw_intf needs its own hw_ctl to program its > + * control path. Hardcode num_ctls to 1 if CWB is enabled > + */ > + if (top->cwb_enabled) > + num_ctls = 1; > + else > + num_ctls = top->num_intf; > > needs_split_display = _dpu_rm_needs_split_display(top); > > diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h > index 0d3adf398bc1..8a2a3705f117 100644 > --- a/drivers/gpu/drm/msm/msm_drv.h > +++ b/drivers/gpu/drm/msm/msm_drv.h > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0-only */ > /* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. > * Copyright (C) 2013 Red Hat > * Author: Rob Clark <robdclark@gmail.com> > @@ -88,6 +89,7 @@ struct msm_display_topology { > u32 num_dspp; > u32 num_dsc; > bool needs_cdm; > + bool cwb_enabled; > }; > > /* Commit/Event thread specific structure */ > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index d53e986eee54..a7850bf844db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1176,6 +1176,8 @@ static struct msm_display_topology dpu_crtc_get_topology( dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, &crtc_state->adjusted_mode); + topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); + /* * Datapath topology selection * @@ -1189,9 +1191,9 @@ static struct msm_display_topology dpu_crtc_get_topology( * Add dspps to the reservation requirements if ctm is requested */ - if (topology.num_intf == 2) + if (topology.num_intf == 2 && !topology.cwb_enabled) topology.num_lm = 2; - else if (topology.num_dsc == 2) + else if (topology.num_dsc == 2 && !topology.cwb_enabled) topology.num_lm = 2; else if (dpu_kms->catalog->caps->has_3d_merge) topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 96c80cf9f6ad..04df3056d75a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -371,8 +371,14 @@ static int _dpu_rm_reserve_ctls( int i = 0, j, num_ctls; bool needs_split_display; - /* each hw_intf needs its own hw_ctrl to program its control path */ - num_ctls = top->num_intf; + /* + * For non-CWB mode, each hw_intf needs its own hw_ctl to program its + * control path. Hardcode num_ctls to 1 if CWB is enabled + */ + if (top->cwb_enabled) + num_ctls = 1; + else + num_ctls = top->num_intf; needs_split_display = _dpu_rm_needs_split_display(top); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 0d3adf398bc1..8a2a3705f117 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <robdclark@gmail.com> @@ -88,6 +89,7 @@ struct msm_display_topology { u32 num_dspp; u32 num_dsc; bool needs_cdm; + bool cwb_enabled; }; /* Commit/Event thread specific structure */
Add the cwb_enabled flag to msm_display topology and adjust the toplogy to account for concurrent writeback Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++++++++-- drivers/gpu/drm/msm/msm_drv.h | 2 ++ 3 files changed, 14 insertions(+), 4 deletions(-)