| Message ID | 20240926074755.22176-2-Hermes.Wu@ite.com.tw (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | fix HDCP CTS fail items and add MCCS support | expand |
On Thu, Sep 26, 2024 at 03:47:51PM GMT, Hermes Wu wrote: > From: Hermes Wu <Hermes.wu@ite.com.tw> > > The hardware aux fifo is 16 byte Nit: AUX, FIFO > > Change definition of AUX_FIFO_MAX_SIZE to 16 > > > Nit: no need for so many empty lines. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver") > Signed-off-by: Hermes Wu <Hermes.wu@ite.com.tw> > --- > drivers/gpu/drm/bridge/ite-it6505.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c > index f372c05360f2..28a8043229d3 100644 > --- a/drivers/gpu/drm/bridge/ite-it6505.c > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > @@ -300,7 +300,7 @@ > #define MAX_CR_LEVEL 0x03 > #define MAX_EQ_LEVEL 0x03 > #define AUX_WAIT_TIMEOUT_MS 15 > -#define AUX_FIFO_MAX_SIZE 32 > +#define AUX_FIFO_MAX_SIZE 16 > #define PIXEL_CLK_DELAY 1 > #define PIXEL_CLK_INVERSE 0 > #define ADJUST_PHASE_THRESHOLD 80000 > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index f372c05360f2..28a8043229d3 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -300,7 +300,7 @@ #define MAX_CR_LEVEL 0x03 #define MAX_EQ_LEVEL 0x03 #define AUX_WAIT_TIMEOUT_MS 15 -#define AUX_FIFO_MAX_SIZE 32 +#define AUX_FIFO_MAX_SIZE 16 #define PIXEL_CLK_DELAY 1 #define PIXEL_CLK_INVERSE 0 #define ADJUST_PHASE_THRESHOLD 80000