From patchwork Thu Oct 3 20:01:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Wentland X-Patchwork-Id: 13821529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70409CF34C5 for ; Thu, 3 Oct 2024 20:03:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7214C10E97F; Thu, 3 Oct 2024 20:02:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.b="netLFOyW"; dkim-atps=neutral Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2062.outbound.protection.outlook.com [40.107.243.62]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE70D10E944; Thu, 3 Oct 2024 20:01:55 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iC4PpH3WwtIJ+GmG78MRiYyNWjwzFYvaUfLllXd/Z9Gh3+PNeQKjxzoFOU9aSZ2IeVfbFP6yLiw/tkCuQfc5tNFNExdoLADfSeNkyQQnHWvbprCu1grwm3F9+Oib76vqdGnbRekNbIhz30zIKVqDjYaTRuhLVbgwXkCouSNB4Wx48Vps7z1L3Ug21Dftfw3o40JyZWS+x+EZAb3AJ8hXq+RsaZQ14DcdqdjObwMLx5nn/PTNl2rNaDVdb6ddeDxM/+tgvQqS5X4vTGbs4NoM7eZDglmZzjGZYqGoCo3K56MsHq0pVI9ZHbfP+bMkG6k7EHbtS+sMu5SFR2zxUP0mhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zz2T/towOpHElCA0E1k7JI+pJV1DUeILq1fMdY4fqFo=; b=I+jUzg7UnhaMVYN/ejkLykWk2dCg4hlT6bZ6V+zrln0gar4uoUNUhFeGtnYoOYGLGYQa16atEU9ufFNgCpknj1/vhq+2nigXCHKC8furqbNu9AND76j/KlRKdPGsvLUVicT/dINmV/n8BApwsV8G8NL7wNKdoUvSUlAb4iFeZcdFiM4DZdvYqDupa5c6bAysZmogPUsdbHmBzVjMqvuYrcU2eUNGr8ci5H1WfwRuFivFH8FgEMJskltzm5PZ5HyxNNEYi/SFg6vdM/6Md8df1uPm1AE7Cp6TBao3blj9kK2n98lY6I1eeerW6Gvg0HwppuFhSNc1zS0om/ataS86Zg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zz2T/towOpHElCA0E1k7JI+pJV1DUeILq1fMdY4fqFo=; b=netLFOyWdA8mAaHHKqsdUZGTkSVXFSkKtIxvEkKe/Bj4M42WIsp0qvlMM4TTskr10scO7K/L8N4UezRVMfA04XjoeeIWZM7MuHxgQiMHMbxGrQTfWFMboOGvnyV2JLSri4imexsmImjshUbEoLcL5szWQRh7OIvOiJl3e46Ccss= Received: from CH0PR03CA0253.namprd03.prod.outlook.com (2603:10b6:610:e5::18) by IA0PR12MB7774.namprd12.prod.outlook.com (2603:10b6:208:430::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.16; Thu, 3 Oct 2024 20:01:53 +0000 Received: from CH2PEPF00000142.namprd02.prod.outlook.com (2603:10b6:610:e5:cafe::d3) by CH0PR03CA0253.outlook.office365.com (2603:10b6:610:e5::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.18 via Frontend Transport; Thu, 3 Oct 2024 20:01:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CH2PEPF00000142.mail.protection.outlook.com (10.167.244.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8026.11 via Frontend Transport; Thu, 3 Oct 2024 20:01:52 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 3 Oct 2024 15:01:48 -0500 Received: from localhost.localdomain (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 3 Oct 2024 15:01:48 -0500 From: Harry Wentland To: , CC: , Alex Hung , Harry Wentland Subject: [PATCH v6 27/44] drm/amd/display: Add support for sRGB EOTF in DEGAM block Date: Thu, 3 Oct 2024 16:01:09 -0400 Message-ID: <20241003200129.1732122-28-harry.wentland@amd.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241003200129.1732122-1-harry.wentland@amd.com> References: <20241003200129.1732122-1-harry.wentland@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: harry.wentland@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000142:EE_|IA0PR12MB7774:EE_ X-MS-Office365-Filtering-Correlation-Id: 64e6e511-918e-47a8-7985-08dce3e6397c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 8o0vRFvLCBiZk4PPbzjg4GMsj70BnyedMBy1Mk6ENT8rpH7aPUzj7AzPqC2uFeixjW97e+cb34ftEIbbZkJ1svjiYJyB3GoU1YZAjLvjCdhfkXS4mWUDnrxHwOVS0RDyQ1DPt5EmfetMmlzk2W66TLIiMNoRgdsdNKgXJ8KSuCSCYFTRKGvW6f7Q4wdGvKrG5CjKVAkvDhhJDFBqTTwK6VGIF1O/WWhv8vCHurXVrDoJSWnj2i1KuOhVCtw6xXtnwBq0H6QMB/eU5SRVBb5WdWWDL2q5jaoZXHwjq9qxzvAYzHkRdxLPEAU52TQB4z0JlcCU6MBFRv75wiYXhUVURsU5j1lyR/GCL7zLhfDSfWWIoyix4r1IdvQGagZAXxGOWe1oNcFcdhB7Ga4nEVL5ApJDhK16DYRzhEUKPS/wNr0Lc5aK0Fbk5ql/PDoeHPAuG60YBoQD3Qh/W0k3FY07m9mFPACdW80Qy4BdTfpfbH0UViWxYmqmaZ1c3zrLRGEseB5NQKzeC3Ok+F7Uukt2j9+h6Kl+cNRKqEglzAO/5ufY/e50ezP0vHlfMoa0h4l756H/SFmmwgyJrTXlwdA3EB7eeqt2oDtRsZEnxOXI5l+sHsHmlR7jKADsRj+HxFr/4xIJ3/b2muKi8Z3b1r6vh4OvcBsaOvx9gn3u6uel/R1RHPRsI00ZtBO+180c0oTIFBWR2gEPbMa3VkYL2Qy9Rtltaif//hONVcTz/+RNbHJzJYIX1Bz8X8kMcBPFUT6PGN/WvbaEkB+omshJiNbtZvOs4VC83IvRXNHOinh07RO1plXmAyBGYEBUSNjJ3R9ByHn5qV+DVIyouFDpcVZMG6LJDaOpbEDCul6R2GW9OsAv3XzgABJqXSTJ8Bsqy5nh0CaNJr/6sU1tlBnE0kCK0Z4bCOh5p8GZ/78v3oNURcvufh07S07HU4/jrbY639yNyeAvHKIqTjMliDcuaokU/eQF2/vhaz2GbNEY2EYM3ptgMwT8nStwEnbCJRad+dho27Ngit076UgmPNUiGEmov1k0q3yjeek+m/pO+rAJpsbxNq385BgZo1tSDpBKVS7powpisFJjAACZUCbP6wHGMEPP8yVXASxuQfgnXVkNyZpQcdqyPP2mgsqjnXeUIwYZchAzMPuLURkwOaiyzO8EsFXXynbxY1LYRXGNjuUKrNMkyFnYsyjhv2KLdYBWcZ8SdQrmeuteuH6tHQQGaz7LQ4ZMx9JKqy7kLWAQygXVeHnSdlr06pV2MvCa5PxSaCKjXS0lZfk3ilbNNWtKqhLnAdD4+hZyyhRqpqa1zHMhfO9+WMFIZpPII9tbq4V1akiIpd+jGagZsZZzMhOhAK9YXzNdpqqL2s8ZmAJhwSv5ymbTAVh60n94oAUfjzuplVCC X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2024 20:01:52.4803 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64e6e511-918e-47a8-7985-08dce3e6397c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000142.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7774 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Alex Hung Expose one 1D curve colorop with support for DRM_COLOROP_1D_CURVE_SRGB_EOTF and program HW to perform the sRGB transform when the colorop is not in bypass. With this change the following IGT test passes: kms_colorop --run plane-XR30-XR30-srgb_eotf The color pipeline now consists of a single colorop: 1. 1D curve colorop w/ sRGB EOTF Signed-off-by: Alex Hung Signed-off-by: Harry Wentland Co-developed-by: Harry Wentland --- v6: - cleanup if colorop alloc or init fails .../gpu/drm/amd/display/amdgpu_dm/Makefile | 3 +- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 88 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 71 +++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_colorop.h | 34 +++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 10 +++ 5 files changed, 205 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h -- 2.46.2 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile index ab2a97e354da..46158d67ab12 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile @@ -38,7 +38,8 @@ AMDGPUDM = \ amdgpu_dm_pp_smu.o \ amdgpu_dm_psr.o \ amdgpu_dm_replay.o \ - amdgpu_dm_wb.o + amdgpu_dm_wb.o \ + amdgpu_dm_colorop.o ifdef CONFIG_DRM_AMD_DC_FP AMDGPUDM += dc_fpu.o diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index ebabfe3a512f..adb1e4b3522d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -668,6 +668,19 @@ amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) } } +static enum dc_transfer_func_predefined +amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf) +{ + switch (tf) + { + case DRM_COLOROP_1D_CURVE_SRGB_EOTF: + case DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF: + return TRANSFER_FUNCTION_SRGB; + default: + return TRANSFER_FUNCTION_LINEAR;; + } +} + static void __to_dc_lut3d_color(struct dc_rgb *rgb, const struct drm_color_lut lut, int bit_precision) @@ -1137,6 +1150,59 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, return 0; } +static int +__set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state, + struct drm_colorop_state *colorop_state) +{ + struct dc_transfer_func *tf = &dc_plane_state->in_transfer_func; + struct drm_colorop *colorop = colorop_state->colorop; + struct drm_device *drm = colorop->dev; + + if (colorop->type != DRM_COLOROP_1D_CURVE && + colorop_state->curve_1d_type != DRM_COLOROP_1D_CURVE_SRGB_EOTF) + return -EINVAL; + + if (colorop_state->bypass) { + tf->type = TF_TYPE_BYPASS; + tf->tf = TRANSFER_FUNCTION_LINEAR; + return 0; + } + + drm_dbg(drm, "Degamma colorop with ID: %d\n", colorop->base.id); + + tf->type = TF_TYPE_PREDEFINED; + tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type); + + return 0; +} + +static int +__set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state, + struct drm_colorop *colorop) +{ + struct drm_colorop *old_colorop; + struct drm_colorop_state *colorop_state = NULL, *new_colorop_state; + struct drm_atomic_state *state = plane_state->state; + int i = 0; + + old_colorop = colorop; + + /* 1st op: 1d curve - degamma */ + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { + if (new_colorop_state->colorop == old_colorop && + new_colorop_state->curve_1d_type == DRM_COLOROP_1D_CURVE_SRGB_EOTF) { + colorop_state = new_colorop_state; + break; + } + } + + if (!colorop_state) + return -EINVAL; + + return __set_colorop_in_tf_1d_curve(dc_plane_state, colorop_state); +} + static int amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) @@ -1187,6 +1253,25 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, return 0; } +static int +amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state) +{ + struct drm_colorop *colorop = plane_state->color_pipeline; + int ret; + + /* 1D Curve - DEGAM TF */ + if (!colorop) { + return -EINVAL; + } + + ret = __set_dm_plane_colorop_degamma(plane_state, dc_plane_state, colorop); + if (ret) + return ret; + + return 0; +} + /** * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. * @crtc: amdgpu_dm crtc state @@ -1283,5 +1368,8 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, dc_plane_state->input_csc_color_matrix.enable_adjustment = false; } + if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state)) + return 0; + return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c new file mode 100644 index 000000000000..c0134e8cf2e5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include +#include +#include + +#include "amdgpu_dm_colorop.h" + +const u64 amdgpu_dm_supported_degam_tfs = + BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF); + +#define MAX_COLOR_PIPELINE_OPS 10 + +int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list) +{ + struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; + struct drm_device *dev = plane->dev; + int ret; + int i = 0; + + memset(ops, 0, sizeof(ops)); + + /* 1D curve - DEGAM TF */ + ops[i] = kzalloc(sizeof(struct drm_colorop), GFP_KERNEL); + if (!ops[i]) { + DRM_ERROR("KMS: Failed to allocate colorop\n"); + ret = -ENOMEM; + goto cleanup; + } + + ret = drm_colorop_curve_1d_init(dev, ops[i], plane, amdgpu_dm_supported_degam_tfs); + if (ret) + goto cleanup; + + list->type = ops[i]->base.id; + list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[i]->base.id); + + return 0; + +cleanup: + for (; i >= 0; i--) + if (ops[i]) + kfree(ops[i]); + + return ret; +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h new file mode 100644 index 000000000000..f16de6a9fbde --- /dev/null +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __AMDGPU_DM_COLOROP_H__ +#define __AMDGPU_DM_COLOROP_H__ + +extern const u64 amdgpu_dm_supported_degam_tfs; + +int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list); + +#endif /* __AMDGPU_DM_COLOROP_H__*/ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 1bfb9f340c24..78c749ce1bd0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -36,6 +36,7 @@ #include "amdgpu_display.h" #include "amdgpu_dm_trace.h" #include "amdgpu_dm_plane.h" +#include "amdgpu_dm_colorop.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" @@ -1763,10 +1764,19 @@ dm_plane_init_colorops(struct drm_plane *plane) { struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES]; int len = 0; + int ret; if (plane->type == DRM_PLANE_TYPE_CURSOR) return 0; + /* initialize default pipeline */ + ret = amdgpu_dm_initialize_default_pipeline(plane, &(pipelines[len])); + if (ret) { + DRM_ERROR("Failed to create color pipeline for plane %d: %d\n", plane->base.id, ret); + return ret; + } + len++; + /* Create COLOR_PIPELINE property and attach */ drm_plane_create_color_pipeline_property(plane, pipelines, len);