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Thu, 3 Oct 2024 15:01:51 -0500 From: Harry Wentland To: , CC: , Harry Wentland Subject: [PATCH v6 33/44] drm/amd/display: Add support for BT.709 and BT.2020 TFs Date: Thu, 3 Oct 2024 16:01:15 -0400 Message-ID: <20241003200129.1732122-34-harry.wentland@amd.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241003200129.1732122-1-harry.wentland@amd.com> References: <20241003200129.1732122-1-harry.wentland@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: harry.wentland@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|SA1PR12MB8919:EE_ X-MS-Office365-Filtering-Correlation-Id: c4ea46ee-fef7-4fa0-408c-08dce3e63a68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: UxASvz8F10QEaEU/eMIdzCHzTgx7bhnJjNTKH/ee/lCd5CUW8Z5C7Vv2/46Hg7HcnsPHts1bkeKU+7YYNkx8j3AwF2yy8EdWk8qMgf23/jUZ/fpr2iJ/WC7IhX+OaVIUKcBrUDoIcd6av34ftpwj1DBNR/dp84o6C0kSKZijH7LJpT5qIEX/kvL0N6f4SpEmTjzp8YjZW+xRx7X7HW/ctiV4jyLQBSJqe6cS/D2sGK+180ZcqIUwm/Biw+9q82l3TUOkiat87yUniWubSWpJaeNcW47cXvSawkWSwgdnt5K6VomV9HB2F1rcqsssaMHrknHaHDUfkZi7bW4f4yymhchsHCS+qYbE0WoqKABJPUojjCuEN7fcOJNozcvptR+mxqkzvgnzhAgE9ELG3gNTE79RXqrnMBji9UrCB9aCcp1hwcQj07J8u4Xq1eQnlA6gicTEx9eKqt4XpbCNCPvZKHmojLNz6IGNtfvXXiSlcTpDDGtwchqD7gzDR1ZBdWIMi4ANlGBfpxQEcpXHmq+3DX91qa7J0HPDBCoez5cGpO7Yc1i8ZES4oRQssy53MnKm94NR1HXNINpfWzwap5g/dNgVaAkWhKCd+N8hfYJRlsFQ9lP+Og4xE8hbcufcbJF9DmpkJwy8e4Yl1jCVBoMnFSdNdo7PUKQPWn9/uIpMbse6UBrxtJBzDwMlsfbcl+mQHY1ZarwxguVNEX2JTHt67Srw5rspu0TDtoG6KLUjVX0Qo6iJ7GV+nuQJttDoI/+qkX6uLZd32LmeVLq4Cz1uBD21XSzSmInkiBqEoYlB3DOjDLEotxr31cieO8Rukjetu6AtphHsrbxoT5WQVpE8g994ncXXlvuhT2zYqvwQxsXG0wEfN68MSU2mtTH92rKZrKKEkxub38B1HJT+4LZbi1m+z+EMrIPW6ET+POmt1qXZSBkBgQrhv4vDog3x7fm3IOOpkciDgTdmtyy3ZlaC8FO8duCrkKskqlzZ91CJksFnbfPpAw6POj8gqEU28paYueNUAnx8HqBFSqhdR6MNtGHTm8mkd74IaxFdxDP7j4b8oEqyucYgzKCskAejBkUH8MibvLRuZuO5Zvup732tYP+Y6kXBDFOAq4Q1Z5EQ49qsGLzcWO7TCJDke0wgx4oeXfRABJTNvMtvpmgE50R5B/nt3zTOBormpwHfehZ1dhTr7KBXdLn+vi+tGDoCVt3lwXzizAhDIxzgFyJPmXUP1JDRFf/5KPn9zftIXyJzQvfux+h8X7JjL3r6iQQDSvwN62aBJgh9TNhQXvvTRJNozhP+74cfx6ble7xQjyDdCSEHgyaqvt85FXyEdbb6GChL4YV6WW7H2TMMnR9R12ffz796FYjRUOQoajdmmnz6FiJOhMHeGa7A44oUBOIGhmGS X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2024 20:01:54.0411 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4ea46ee-fef7-4fa0-408c-08dce3e63a68 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8919 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This adds support for the BT.709/BT.2020 transfer functions on all current 1D curve plane colorops, i.e., on DEGAM, SHAPER, and BLND blocks. With this change the following IGT subtests pass: kms_colorop --run plane-XR30-XR30-bt2020_inv_oetf kms_colorop --run plane-XR30-XR30-bt2020_oetf Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 11 ++++++++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 10 +++++++--- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index d4ef20bc2be5..69d41b32f529 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -677,6 +677,9 @@ amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf) case DRM_COLOROP_1D_CURVE_SRGB_EOTF: case DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF: return TRANSFER_FUNCTION_SRGB; + case DRM_COLOROP_1D_CURVE_BT2020_INV_OETF: + case DRM_COLOROP_1D_CURVE_BT2020_OETF: + return TRANSFER_FUNCTION_BT709; case DRM_COLOROP_1D_CURVE_PQ_125_EOTF: case DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF: return TRANSFER_FUNCTION_PQ; @@ -1285,8 +1288,10 @@ __set_colorop_1d_curve_blend_tf_lut(struct dc_plane_state *dc_plane_state, const struct drm_color_lut *blend_lut; uint32_t blend_size; - if (colorop->type != DRM_COLOROP_1D_CURVE && - colorop_state->curve_1d_type != DRM_COLOROP_1D_CURVE_SRGB_EOTF) + if (colorop->type != DRM_COLOROP_1D_CURVE) + return -EINVAL; + + if (!(BIT(colorop_state->curve_1d_type) & amdgpu_dm_supported_blnd_tfs)) return -EINVAL; if (colorop_state->bypass) { @@ -1322,7 +1327,7 @@ __set_dm_plane_colorop_blend(struct drm_plane_state *plane_state, /* 3nd op: 1d curve - blend */ for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { if (new_colorop_state->colorop == old_colorop && - new_colorop_state->curve_1d_type == DRM_COLOROP_1D_CURVE_SRGB_EOTF) { + (BIT(new_colorop_state->curve_1d_type) & amdgpu_dm_supported_blnd_tfs)) { colorop_state = new_colorop_state; break; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c index 0578f33c8422..7fd274dc89b7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c @@ -33,14 +33,18 @@ const u64 amdgpu_dm_supported_degam_tfs = BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) | - BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF); + BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) | + BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF); const u64 amdgpu_dm_supported_shaper_tfs = BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) | - BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF); + BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) | + BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF); const u64 amdgpu_dm_supported_blnd_tfs = - BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF); + BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) | + BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) | + BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF); #define MAX_COLOR_PIPELINE_OPS 10