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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-45da74e9fdasm9072351cf.31.2024.10.05.07.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 07:43:08 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Konrad Dybcio , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER for Qualcomm display hardware), dri-devel@lists.freedesktop.org (open list:DRM DRIVER for Qualcomm display hardware), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] drm/msm/dsi: fix 32-bit signed integer extension in pclk_rate calculation Date: Sat, 5 Oct 2024 10:38:10 -0400 Message-ID: <20241005143818.2036-2-jonathan@marek.ca> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241005143818.2036-1-jonathan@marek.ca> References: <20241005143818.2036-1-jonathan@marek.ca> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" When (mode->clock * 1000) is larger than (1<<31), int to unsigned long conversion will sign extend the int to 64 bits and the pclk_rate value will be incorrect. Fix this by making the result of the multiplication unsigned. Note that above (1<<32) would still be broken and require more changes, but its unlikely anyone will need that anytime soon. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 1205aa398e445..a98d24b7cb00b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -550,7 +550,7 @@ static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, { unsigned long pclk_rate; - pclk_rate = mode->clock * 1000; + pclk_rate = mode->clock * 1000u; if (dsc) pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc);