| Message ID | 20241007022834.4609-1-moudy.ho@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v5] dt-bindings: display: mediatek: split: add subschema property constraints | expand |
On Mon, Oct 07, 2024 at 10:28:34AM +0800, Moudy Ho wrote: > The display node in mt8195.dtsi was triggering a CHECK_DTBS error due > to an excessively long 'clocks' property: > display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long > > To resolve this issue, the constraints for 'clocks' and > other properties within the subschemas will be reinforced. > > Fixes: 739058a9c5c3 ("dt-bindings: display: mediatek: split: add compatible for MT8195") > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > -- > This is based on [v2] dt-bindings: display: mediatek: split: add clocks count constraint for MT8195 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi, Moudy: Moudy Ho <moudy.ho@mediatek.com> 於 2024年10月7日 週一 上午10:28寫道： > > The display node in mt8195.dtsi was triggering a CHECK_DTBS error due > to an excessively long 'clocks' property: > display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long > > To resolve this issue, the constraints for 'clocks' and > other properties within the subschemas will be reinforced. Applied to mediatek-drm-fixes [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes Regards, Chun-Kuang. > > Fixes: 739058a9c5c3 ("dt-bindings: display: mediatek: split: add compatible for MT8195") > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > -- > This is based on [v2] dt-bindings: display: mediatek: split: add clocks count constraint for MT8195 > > Changes since v4: > - Eliminate the possibility of varying quantities in the 'clocks' > property of mt8195. > - Move the constraint for 'power-domains' to the top-level. > > Changes since v3: > - Correct the compatible name for the mt8173 split in the subschema. > > Changes since v2: > - Revise the commit message. > - Enhance the descriptions of 'clocks'. > - Strengthen the conditions within the subschema. > > Changes since v1: > - Adding functional descriptions and quantity restrictions. > --- > .../display/mediatek/mediatek,split.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml > index e4affc854f3d..4b6ff546757e 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml > @@ -38,6 +38,7 @@ properties: > description: A phandle and PM domain specifier as defined by bindings of > the power controller specified by phandle. See > Documentation/devicetree/bindings/power/power-domain.yaml for details. > + maxItems: 1 > > mediatek,gce-client-reg: > description: > @@ -57,6 +58,9 @@ properties: > clocks: > items: > - description: SPLIT Clock > + - description: Used for interfacing with the HDMI RX signal source. > + - description: Paired with receiving HDMI RX metadata. > + minItems: 1 > > required: > - compatible > @@ -72,9 +76,24 @@ allOf: > const: mediatek,mt8195-mdp3-split > > then: > + properties: > + clocks: > + minItems: 3 > + > required: > - mediatek,gce-client-reg > > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8173-disp-split > + > + then: > + properties: > + clocks: > + maxItems: 1 > + > additionalProperties: false > > examples: > -- > 2.34.1 >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index e4affc854f3d..4b6ff546757e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -38,6 +38,7 @@ properties: description: A phandle and PM domain specifier as defined by bindings of the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + maxItems: 1 mediatek,gce-client-reg: description: @@ -57,6 +58,9 @@ properties: clocks: items: - description: SPLIT Clock + - description: Used for interfacing with the HDMI RX signal source. + - description: Paired with receiving HDMI RX metadata. + minItems: 1 required: - compatible @@ -72,9 +76,24 @@ allOf: const: mediatek,mt8195-mdp3-split then: + properties: + clocks: + minItems: 3 + required: - mediatek,gce-client-reg + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-disp-split + + then: + properties: + clocks: + maxItems: 1 + additionalProperties: false examples:
The display node in mt8195.dtsi was triggering a CHECK_DTBS error due to an excessively long 'clocks' property: display@14f06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long To resolve this issue, the constraints for 'clocks' and other properties within the subschemas will be reinforced. Fixes: 739058a9c5c3 ("dt-bindings: display: mediatek: split: add compatible for MT8195") Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> -- This is based on [v2] dt-bindings: display: mediatek: split: add clocks count constraint for MT8195 Changes since v4: - Eliminate the possibility of varying quantities in the 'clocks' property of mt8195. - Move the constraint for 'power-domains' to the top-level. Changes since v3: - Correct the compatible name for the mt8173 split in the subschema. Changes since v2: - Revise the commit message. - Enhance the descriptions of 'clocks'. - Strengthen the conditions within the subschema. Changes since v1: - Adding functional descriptions and quantity restrictions. --- .../display/mediatek/mediatek,split.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)