| Message ID | 20241010093132.235177-1-manikandan.m@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: atmel-hlcdc: bypass LCDC pixel clock divider when using LCDC Generic Clock | expand |
On Thu, 10 Oct 2024, Manikandan Muralidharan wrote: > In sam9x7 SoC where XLCDC IP is used,add support to bypass the LCDC pixel > clock divider when LCDC Generic clock is enabled.Used to match > and drive the panel requested Pixel clock. > > Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> > --- > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 8 +++++++- > include/linux/mfd/atmel-hlcdc.h | 1 + Acked-by: Lee Jones <lee@kernel.org> > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > index 0f7ffb3ced20..c54770cecaa8 100644 > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > @@ -146,13 +146,19 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) > > if (div_low >= 2 && > (10 * (prate / div_low - mode_rate) < > - (mode_rate - prate / div))) > + (mode_rate - prate / div))) { > /* > * At least 10 times better when using a higher > * frequency than requested, instead of a lower. > * So, go with that. > */ > div = div_low; > + } else { > + if (crtc->dc->desc->is_xlcdc) { > + cfg |= ATMEL_XLCDC_CLKBYP; > + mask |= ATMEL_XLCDC_CLKBYP; > + } > + } > } > > cfg |= ATMEL_HLCDC_CLKDIV(div); > diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h > index 80d675a03b39..982f494e6307 100644 > --- a/include/linux/mfd/atmel-hlcdc.h > +++ b/include/linux/mfd/atmel-hlcdc.h > @@ -44,6 +44,7 @@ > #define ATMEL_XLCDC_HEO_UPDATE BIT(3) > > #define ATMEL_HLCDC_CLKPOL BIT(0) > +#define ATMEL_XLCDC_CLKBYP BIT(1) > #define ATMEL_HLCDC_CLKSEL BIT(2) > #define ATMEL_HLCDC_CLKPWMSEL BIT(3) > #define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i)) > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 0f7ffb3ced20..c54770cecaa8 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -146,13 +146,19 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) if (div_low >= 2 && (10 * (prate / div_low - mode_rate) < - (mode_rate - prate / div))) + (mode_rate - prate / div))) { /* * At least 10 times better when using a higher * frequency than requested, instead of a lower. * So, go with that. */ div = div_low; + } else { + if (crtc->dc->desc->is_xlcdc) { + cfg |= ATMEL_XLCDC_CLKBYP; + mask |= ATMEL_XLCDC_CLKBYP; + } + } } cfg |= ATMEL_HLCDC_CLKDIV(div); diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h index 80d675a03b39..982f494e6307 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -44,6 +44,7 @@ #define ATMEL_XLCDC_HEO_UPDATE BIT(3) #define ATMEL_HLCDC_CLKPOL BIT(0) +#define ATMEL_XLCDC_CLKBYP BIT(1) #define ATMEL_HLCDC_CLKSEL BIT(2) #define ATMEL_HLCDC_CLKPWMSEL BIT(3) #define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i))
In sam9x7 SoC where XLCDC IP is used,add support to bypass the LCDC pixel clock divider when LCDC Generic clock is enabled.Used to match and drive the panel requested Pixel clock. Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 8 +++++++- include/linux/mfd/atmel-hlcdc.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-)