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Fri, 11 Oct 2024 01:21:51 -0500 Received: from JesseDEV.guestwireless.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 11 Oct 2024 01:21:44 -0500 From: To: , CC: , Christian Koenig , "Jesse.zhang@amd.com" , Jesse Zhang Subject: [PATCH 2/2] drm/amdgpu: add the ring id schedule module parameter for amdgpu Date: Fri, 11 Oct 2024 14:21:36 +0800 Message-ID: <20241011062136.1019695-2-jesse.zhang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241011062136.1019695-1-jesse.zhang@amd.com> References: <20241011062136.1019695-1-jesse.zhang@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: jesse.zhang@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004686:EE_|CH3PR12MB8402:EE_ X-MS-Office365-Filtering-Correlation-Id: 08ea0a00-c082-4c06-fe3b-08dce9bcff0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2024 06:21:52.1242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08ea0a00-c082-4c06-fe3b-08dce9bcff0b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004686.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8402 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: "Jesse.zhang@amd.com" Added ring id schedule to switch scheduling policy when cs submits. Schedule the ring by setting the ring id. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 48c9b9b06905..3fd3e4eeab47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -227,6 +227,7 @@ extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; extern int amdgpu_use_xgmi_p2p; +extern int amdgpu_ring_id_schedule; extern int amdgpu_mtype_local; extern bool enforce_isolation; #ifdef CONFIG_HSA_AMD diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 18887128a973..33658bef5513 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1276,6 +1276,7 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs) { + struct drm_amdgpu_cs_chunk_ib *chunk_ib = p->chunks[0].kdata; struct amdgpu_fpriv *fpriv = p->filp->driver_priv; struct amdgpu_job *leader = p->gang_leader; struct amdgpu_bo_list_entry *e; @@ -1285,8 +1286,12 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, uint64_t seq; int r; - for (i = 0; i < p->gang_size; ++i) - drm_sched_job_arm(&p->jobs[i]->base, -1); + for (i = 0; i < p->gang_size; ++i) { + if (amdgpu_ring_id_schedule) + drm_sched_job_arm(&p->jobs[i]->base, chunk_ib->ring); + else + drm_sched_job_arm(&p->jobs[i]->base, -1); + } for (i = 0; i < p->gang_size; ++i) { struct dma_fence *fence; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 680e44fdee6e..55fba9e93a8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -221,6 +221,7 @@ int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1; int amdgpu_smartshift_bias; int amdgpu_use_xgmi_p2p = 1; +int amdgpu_ring_id_schedule = 0; int amdgpu_vcnfw_log; int amdgpu_sg_display = -1; /* auto */ int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; @@ -740,6 +741,13 @@ MODULE_PARM_DESC(use_xgmi_p2p, "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); +/** + * DOC: ring_id_schedule (int) + * Enables/disables ring id schedule interface (0 = disable, 1 = enable, -1 auto (default)) + */ +MODULE_PARM_DESC(ring_id_schedule, + "Enable ring id schedule interface(0 = disable, 1 = enable, -1 auto (default))"); +module_param_named(ring_id_schedule, amdgpu_ring_id_schedule, int, 0644); #ifdef CONFIG_HSA_AMD /**