From patchwork Mon Oct 21 14:07:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13844244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA9CED15D96 for ; Mon, 21 Oct 2024 14:08:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 37CC310E527; Mon, 21 Oct 2024 14:08:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="dyJ9w6Ot"; dkim-atps=neutral Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9141710E520 for ; Mon, 21 Oct 2024 14:08:18 +0000 (UTC) Received: from [127.0.1.1] (91-157-155-49.elisa-laajakaista.fi [91.157.155.49]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id A51D11775; Mon, 21 Oct 2024 16:06:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1729519591; bh=VBitCg4mmzcbGyGk6q4vLoLZGA6NGjSGxDJCUaNRvRA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dyJ9w6Oty908otkRxZOKWO1PS3cEDZdAKt2iIRMvLHuGuuCX/0JwLMK7d6NWRnI/j qjbgEVn9R6ktyaVu93CSVA1IglJPShVcR/OSXw0dD190svCH3FldrVTZbfN+Xsmj9w wa/8z2popAW6glKGFqdfmy0/dOgsZcijA39X0TZM= From: Tomi Valkeinen Date: Mon, 21 Oct 2024 17:07:45 +0300 Subject: [PATCH 1/7] drm/tidss: Fix issue in irq handling causing irq-flood issue MIME-Version: 1.0 Message-Id: <20241021-tidss-irq-fix-v1-1-82ddaec94e4a@ideasonboard.com> References: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> In-Reply-To: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> To: Devarsh Thakkar , Jyri Sarha Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jonathan Cormier , Tomi Valkeinen , Bin Liu , stable@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3147; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=VBitCg4mmzcbGyGk6q4vLoLZGA6NGjSGxDJCUaNRvRA=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBnFmBMHTozIfIAbjm5ocXIG5ei/8JY10fx5WH+c u6fVWtNOfuJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZxZgTAAKCRD6PaqMvJYe 9YSIEACmQz+oDjXeahJ5zI+JsbI5Ax7kejJ0nkUwa25a2Xm+kcbrjRgR6iJJs93GyuccBI/d9iB 865nFZO4QQNUe8zVxy1AoftrDQMGrephfAXmMhg+dy9QPD+OBj9dHfoZwzX9tOM8ZgxOAH6qYpp czJ1xC/IWbZZcjmm1+/hn9KmLSyEAYntDr1qd5SloR0jcn3dQBz+F3LoQPyR+P2aH2uXBYMWIYc 76ZEN+/PD/bAk49yLxcfAEPk7yqE2bquxoiCjDliokSxEH6gkJgI2Vn6yGx9lNpJazjm0AOzcz1 SYUK2d7GU1HjtGcsylsHT5e3PJ6J7+U7dhjEtq8NuyqqqkLtL729rh5tPGyOP01KFum83ugAXBO 5iW+fXI9RTiILT5nBLpuJWFJyKtR5KU0dbDYIDIO48VLr4LlcwX0LpuJh71yIFeUo+lAZRx+FuE +riqBc9puFiw+U8DzR9lXenUWfaxicMPhVz/VQ1CmlDIds+0J3ypwH4U4hSl+nYCeIM6vkxHMpg UDPb1msyY9VquNeuIG/FAN9ShOdvmApZtU+iUKH4gdcyPOb0b4AWOR/YwKyUVJNQN4Ki1CWrTJ4 dpPTU+C04jDQmr1AiOwSeUlawYGMm1mna8uuJed5FY4kyZc9BfBYf4UZOXGnD/SNc0lTYBYy0x/ FDag+XhxTw7HC/w== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It has been observed that sometimes DSS will trigger an interrupt and the top level interrupt (DISPC_IRQSTATUS) is not zero, but the VP and VID level interrupt-statuses are zero. As the top level irqstatus is supposed to tell whether we have VP/VID interrupts, the thinking of the driver authors was that this particular case could never happen. Thus the driver only clears the DISPC_IRQSTATUS bits which has corresponding interrupts in VP/VID status. So when this issue happens, the driver will not clear DISPC_IRQSTATUS, and we get an interrupt flood. It is unclear why the issue happens. It could be a race issue in the driver, but no such race has been found. It could also be an issue with the HW. However a similar case can be easily triggered by manually writing to DISPC_IRQSTATUS_RAW. This will forcibly set a bit in the DISPC_IRQSTATUS and trigger an interrupt, and as the driver never clears the bit, we get an interrupt flood. To fix the issue, always clear DISPC_IRQSTATUS. The concern with this solution is that if the top level irqstatus is the one that triggers the interrupt, always clearing DISPC_IRQSTATUS might leave some interrupts unhandled if VP/VID interrupt statuses have bits set. However, testing shows that if any of the irqstatuses is set (i.e. even if DISPC_IRQSTATUS == 0, but a VID irqstatus has a bit set), we will get an interrupt. Signed-off-by: Tomi Valkeinen Co-developed-by: Bin Liu Signed-off-by: Bin Liu Co-developed-by: Devarsh Thakkar Signed-off-by: Devarsh Thakkar Co-developed-by: Jonathan Cormier Signed-off-by: Jonathan Cormier Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem") Cc: stable@vger.kernel.org Tested-by: Jonathan Cormier Tested-by: Jonathan Cormier --- drivers/gpu/drm/tidss/tidss_dispc.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 1ad711f8d2a8..f81111067578 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -780,24 +780,20 @@ static void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) { unsigned int i; - u32 top_clear = 0; for (i = 0; i < dispc->feat->num_vps; ++i) { - if (clearmask & DSS_IRQ_VP_MASK(i)) { + if (clearmask & DSS_IRQ_VP_MASK(i)) dispc_k3_vp_write_irqstatus(dispc, i, clearmask); - top_clear |= BIT(i); - } } for (i = 0; i < dispc->feat->num_planes; ++i) { - if (clearmask & DSS_IRQ_PLANE_MASK(i)) { + if (clearmask & DSS_IRQ_PLANE_MASK(i)) dispc_k3_vid_write_irqstatus(dispc, i, clearmask); - top_clear |= BIT(4 + i); - } } if (dispc->feat->subrev == DISPC_K2G) return; - dispc_write(dispc, DISPC_IRQSTATUS, top_clear); + /* always clear the top level irqstatus */ + dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS)); /* Flush posted writes */ dispc_read(dispc, DISPC_IRQSTATUS);