| Message ID | 20241021-tidss-irq-fix-v1-6-82ddaec94e4a@ideasonboard.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/tidss: Interrupt fixes and cleanups | expand |
On Mon, Oct 21, 2024 at 10:08 AM Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> wrote: > > From: Devarsh Thakkar <devarsht@ti.com> > > The driver has a spinlock for protecting the irq_masks field and irq > enable registers. However, the driver misses protecting the irq status > registers which can lead to races. > > Take the spinlock when accessing irqstatus too. > > Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem") > Cc: stable@vger.kernel.org > Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > [Tomi: updated the desc] > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> > --- > drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++++ > drivers/gpu/drm/tidss/tidss_irq.c | 2 ++ > 2 files changed, 6 insertions(+) Reviewed-by: Jonathan Cormier <jcormier@criticallink.com> Tested an equivalent patch for several weeks. Tested-by: Jonathan Cormier <jcormier@criticallink.com> > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index 515f82e8a0a5..07f5c26cfa26 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -2767,8 +2767,12 @@ static void dispc_init_errata(struct dispc_device *dispc) > */ > static void dispc_softreset_k2g(struct dispc_device *dispc) > { > + unsigned long flags; > + > + spin_lock_irqsave(&dispc->tidss->wait_lock, flags); > dispc_set_irqenable(dispc, 0); > dispc_read_and_clear_irqstatus(dispc); > + spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags); > > for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx) > VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); > diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tidss_irq.c > index 3cc4024ec7ff..8af4682ba56b 100644 > --- a/drivers/gpu/drm/tidss/tidss_irq.c > +++ b/drivers/gpu/drm/tidss/tidss_irq.c > @@ -60,7 +60,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg) > unsigned int id; > dispc_irq_t irqstatus; > > + spin_lock(&tidss->wait_lock); > irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); > + spin_unlock(&tidss->wait_lock); > > for (id = 0; id < tidss->num_crtcs; id++) { > struct drm_crtc *crtc = tidss->crtcs[id]; > > -- > 2.43.0 >
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 515f82e8a0a5..07f5c26cfa26 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -2767,8 +2767,12 @@ static void dispc_init_errata(struct dispc_device *dispc) */ static void dispc_softreset_k2g(struct dispc_device *dispc) { + unsigned long flags; + + spin_lock_irqsave(&dispc->tidss->wait_lock, flags); dispc_set_irqenable(dispc, 0); dispc_read_and_clear_irqstatus(dispc); + spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags); for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx) VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tidss_irq.c index 3cc4024ec7ff..8af4682ba56b 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.c +++ b/drivers/gpu/drm/tidss/tidss_irq.c @@ -60,7 +60,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg) unsigned int id; dispc_irq_t irqstatus; + spin_lock(&tidss->wait_lock); irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); + spin_unlock(&tidss->wait_lock); for (id = 0; id < tidss->num_crtcs; id++) { struct drm_crtc *crtc = tidss->crtcs[id];