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Mon, 21 Oct 2024 06:45:29 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%4]) with mapi id 15.20.8069.027; Mon, 21 Oct 2024 06:45:29 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_jesszhan@quicinc.com, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, sakari.ailus@linux.intel.com, hverkuil@xs4all.nl, tomi.valkeinen@ideasonboard.com, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, thierry.reding@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, sam@ravnborg.org, marex@denx.de, biju.das.jz@bp.renesas.com Subject: [PATCH v3 01/15] arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Set "media_disp2_pix" clock rate to 70MHz Date: Mon, 21 Oct 2024 14:44:32 +0800 Message-Id: <20241021064446.263619-2-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241021064446.263619-1-victor.liu@nxp.com> References: <20241021064446.263619-1-victor.liu@nxp.com> X-ClientProxiedBy: SG2PR03CA0111.apcprd03.prod.outlook.com (2603:1096:4:91::15) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|AM9PR04MB8440:EE_ X-MS-Office365-Filtering-Correlation-Id: f4ed54df-e8fc-4424-e10b-08dcf19bf388 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Set "media_disp2_pix" clock rate to that rate, instead of the original 68.9MHz. The LVDS serial clock is controlled by "media_ldb" clock. It should run at 490MHz(7-fold the pixel clock rate due to single LVDS link). Set "video_pll1" clock rate and "media_ldb" to 490MHz to achieve that. This should be able to suppress this LDB driver warning: [ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Signed-off-by: Liu Ying --- v3: * New patch. .../dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index 30962922b361..2c75da5f064f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -52,7 +52,7 @@ &lcdif2 { &lvds_bridge { /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ - assigned-clock-rates = <482300000>; + assigned-clock-rates = <490000000>; status = "okay"; ports { @@ -70,10 +70,10 @@ &media_blk_ctrl { */ assigned-clock-rates = <500000000>, <200000000>, <0>, /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */ - <68900000>, + <70000000>, <500000000>, - /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */ - <964600000>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */ + <490000000>; }; &pwm4 {