From patchwork Tue Nov 19 14:01:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 13879949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73A69D4415E for ; Tue, 19 Nov 2024 14:13:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E904410E65E; Tue, 19 Nov 2024 14:13:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fI6MbVI2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49E4D10E65F; Tue, 19 Nov 2024 14:13:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732025604; x=1763561604; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8st0GcF0LWZ1MQQer5WMDLRIdMrYVYWR9wmuvEfF6mw=; b=fI6MbVI2jcJ82ZsAue/5eiMWEWhKEK+eNKny/PMVEeEKxyAAzmQwQx8+ TgreLjngzBJnXuagzFc96R8cxSNCEi1Z6lDqox3zOLtgpap3hQqQ1fb6D /gv1uPza9n+N649Wfot4b9MnaMzdIS/8/wMdWdU/RpPZ+sD/ZRY8LTChD Kjg69IkMb/dOgwhO+ej/eOcjycVSYd0JyRn/Mtp8GakRpY1vd/Flf3mBV Y1X9I+cKPTBoD4ni+lC8+U8g2Qnq/rbl1aPTHSxIAS/PdrPRpeJNLZUWi /Go57jzyVkk5MgUJS/uoln3kiPAlavsIO71dovuz9VUY/q3fZtQP6cwiW Q==; X-CSE-ConnectionGUID: FSsTyd3PR0iH9p6M/2ryHg== X-CSE-MsgGUID: WgKcmmb7R7GONZcmW0kKsg== X-IronPort-AV: E=McAfee;i="6700,10204,11261"; a="54526828" X-IronPort-AV: E=Sophos;i="6.12,166,1728975600"; d="scan'208";a="54526828" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 06:13:22 -0800 X-CSE-ConnectionGUID: NbCp7sXRRdqoVguTpcv6aA== X-CSE-MsgGUID: rgreELZBSDyZgnxUZQXs0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,166,1728975600"; d="scan'208";a="94398685" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 06:13:17 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v3 08/10] drm/i915/nvm: add support for access mode Date: Tue, 19 Nov 2024 16:01:10 +0200 Message-ID: <20241119140112.790720-9-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241119140112.790720-1-alexander.usyskin@intel.com> References: <20241119140112.790720-1-alexander.usyskin@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Reviewed-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_nvm.c index 75d3ebe669ff..d88f8b9b5ace 100644 --- a/drivers/gpu/drm/i915/intel_nvm.c +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -10,6 +10,7 @@ #include "intel_nvm.h" #define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = { [0] = { .name = "DESCRIPTOR", }, @@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev) { } +static bool i915_nvm_writeable_override(struct drm_i915_private *i915) +{ + resource_size_t base; + bool writeable_override; + + if (IS_DG1(i915)) { + base = DG1_GSC_HECI2_BASE; + } else if (IS_DG2(i915)) { + base = DG2_GSC_HECI2_BASE; + } else { + drm_err(&i915->drm, "Unknown platform\n"); + return true; + } + + writeable_override = + !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writeable_override) + drm_info(&i915->drm, "NVM access overridden by jumper\n"); + return writeable_override; +} + void intel_nvm_init(struct drm_i915_private *i915) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); @@ -43,7 +66,7 @@ void intel_nvm_init(struct drm_i915_private *i915) nvm = i915->nvm; - nvm->writeable_override = true; + nvm->writeable_override = i915_nvm_writeable_override(i915); nvm->bar.parent = &pdev->resource[0]; nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;