From patchwork Thu Nov 21 04:26:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 13881615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFC56D75BB2 for ; Thu, 21 Nov 2024 04:26:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E8A110E857; Thu, 21 Nov 2024 04:26:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="T93JvMCJ"; dkim-atps=neutral Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5DAC810E857 for ; Thu, 21 Nov 2024 04:26:09 +0000 (UTC) X-UUID: b988652ca7c011ef99858b75a2457dd9-20241121 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=2A1gVmEsv9iSPpIpyfpWVjAEBsuCxHX96ctzdzXQSmE=; b=T93JvMCJqI+w63LDlcpkgPF0ptOSmxlZn4Wz+z6pJT8jN3kBMyLEEsW1D6uvx04YOe0MY2bTEG5/iBk2Y1zR3xWpoHWmZiHz/xEF6EmIVi+/bVfPSG0TNuR1zioJmI1DQhNwE90Cz7JXm7u5P+s04vrYYyg5khfqwp4lplMTKGI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.44, REQID:320a8263-6ae9-4d49-a13b-471ce030b8fe, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:464815b, CLOUDID:d21a8fa0-f395-4dfc-8188-ce2682df7fd8, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0,EDM:-3,IP :nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0, LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: b988652ca7c011ef99858b75a2457dd9-20241121 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1489044708; Thu, 21 Nov 2024 12:26:06 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 21 Nov 2024 12:26:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 21 Nov 2024 12:26:04 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Mauro Carvalho Chehab CC: David Airlie , Simona Vetter , Moudy Ho , , , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH 7/8] drm/mediatek: Add pa_base due to CMDQ API change Date: Thu, 21 Nov 2024 12:26:01 +0800 Message-ID: <20241121042602.32730-8-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241121042602.32730-1-jason-jh.lin@mediatek.com> References: <20241121042602.32730-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To support non-subsys ID hardware on new SoCs, the CMDQ API has been changed to include the pa_base parameter. This change accommodates the new interface requirements. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index edc6417639e6..8d999bfb25b6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -72,7 +72,7 @@ void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, + cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base, cmdq_reg->offset + offset, value); else #endif @@ -85,7 +85,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, + cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base, cmdq_reg->offset + offset, value); else #endif @@ -98,7 +98,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { - cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, + cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, cmdq_reg->pa_base, cmdq_reg->offset + offset, value, mask); } else { #endif