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Thu, 28 Nov 2024 02:25:50 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd2db59sm1265909f8f.11.2024.11.28.02.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:25:50 -0800 (PST) From: Neil Armstrong Date: Thu, 28 Nov 2024 11:25:43 +0100 Subject: [PATCH v3 3/7] drm/msm: adreno: dynamically generate GMU bw table MIME-Version: 1.0 Message-Id: <20241128-topic-sm8x50-gpu-bw-vote-v3-3-81d60c10fb73@linaro.org> References: <20241128-topic-sm8x50-gpu-bw-vote-v3-0-81d60c10fb73@linaro.org> In-Reply-To: <20241128-topic-sm8x50-gpu-bw-vote-v3-0-81d60c10fb73@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3000; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=m6cl+5dS7Bml6VmAVtYBvyewU2newXJK0Ii2eLN6yeQ=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnSEUo6s9LquaLR+t1nEdRJP/ejIjlnSkwxWLYTtMU dqJbcumJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0hFKAAKCRB33NvayMhJ0WxpD/ 4xaJOWThrZMYAhDcrGpuIeGYdU2zQYPNgiJPV8h1MiEz8m7g+ZbjOHJjRX5Lto+HVhMlKjqhiIfIuZ LzMI7RwrC+D6QNFKZiND1klBrhVGXpnkOdqDhO4ZE+lxf5IgF+PtZQi/tWs2k63P2DeAvGzOJxXF2i CJJiud6JioVyBbZvCGomMl3SLnfFkQml7agoY6wyHXz7cITxkth4PD2Mptv8U4HbQ1QPksCOgNLhGh CMrfwwhD5kCztNVBoNSmT+lAo1MlP5lDvU76wwRYBl0dRo8GwesHreB9qz0VTwvf01/GK7K4ktpHj9 B6YKc9H1oNfszwrssRp7mWmmCiHYzwP53gzsruiZNGpeyhbaQx2ZohVm+25+8R5VLupzB7565H49hC eLZdV8V3Xe3diOICPugaNJ2ajlx3oKYfy2yJPFFicOT2NiL8wzKUc9QXIMqCtDVMm2sCznLhrjvs3W 9og//JiUKsRQ8R6prBe7OSh/77TcZVOHmwy0vgTZsJPQk65bw0H+h+FTAfFosgqPhbOMndfn4rUuUn I6RdaTwoEMTLSGYTaRmeuO4eS265TsNRRJ6Tq2aAJrHCO19I5UDeK2rdsGeS6LoqUr6g8/qi/rX0SA JR8RC5oCAqNqEmSC9xXftPesdzwnJtDZIaeLco6R3we3gi3SY1Lf9xrNCaHQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Adreno GPU Management Unit (GMU) can also scale the ddr bandwidth along the frequency and power domain level, but for now we statically fill the bw_table with values from the downstream driver. Only the first entry is used, which is a disable vote, so we currently rely on scaling via the linux interconnect paths. Let's dynamically generate the bw_table with the vote values previously calculated from the OPPs. Those entried will then be used by the GMU when passing the appropriate bandwidth level while voting for a gpu frequency. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 39 ++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index cb8844ed46b29c4569d05eb7a24f7b27e173190f..fe1946650425b749bad483dad1e630bc8be83abc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -621,6 +621,35 @@ static void a740_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) msg->cnoc_cmds_data[1][0] = 0x60000001; } +static void a740_generate_bw_table(const struct a6xx_info *info, struct a6xx_gmu *gmu, + struct a6xx_hfi_msg_bw_table *msg) +{ + unsigned int i, j; + + msg->ddr_wait_bitmask = 0x7; + + for (i = 0; i < GMU_MAX_BCMS; i++) { + if (!info->bcms[i].name) + break; + msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcms[i].name); + } + msg->ddr_cmds_num = i; + + for (i = 0; i < gmu->nr_gpu_bws; ++i) + for (j = 0; j < msg->ddr_cmds_num; j++) + msg->ddr_cmds_data[i][j] = gmu->gpu_ib_votes[i][j]; + msg->bw_level_num = gmu->nr_gpu_bws; + + /* TODO also generate CNOC commands */ + + msg->cnoc_cmds_num = 1; + msg->cnoc_wait_bitmask = 0x1; + + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[1][0] = 0x60000001; +} + static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ @@ -664,6 +693,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) struct a6xx_hfi_msg_bw_table *msg; struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; if (gmu->bw_table) goto send; @@ -690,9 +720,12 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) a690_build_bw_table(msg); else if (adreno_is_a730(adreno_gpu)) a730_build_bw_table(msg); - else if (adreno_is_a740_family(adreno_gpu)) - a740_build_bw_table(msg); - else + else if (adreno_is_a740_family(adreno_gpu)) { + if (info->bcms && gmu->nr_gpu_bws > 1) + a740_generate_bw_table(info, gmu, msg); + else + a740_build_bw_table(msg); + } else a6xx_build_bw_table(msg); gmu->bw_table = msg;