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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2024 10:38:23.8003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1202fbe9-9a6b-47be-1980-08dd11f4485a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9524 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Yonatan Maman Handle P2P DMA mapping errors when the transaction requires traversing an inaccessible host bridge that is not in the allowlist: - In `populate_mtt`, if a P2P mapping fails, the `HMM_PFN_ALLOW_P2P` flag is cleared only for the PFNs that returned a mapping error. - In `pagefault_real_mr`, if a P2P mapping error occurs, the mapping is retried with the `HMM_PFN_ALLOW_P2P` flag only for the PFNs that didn't fail, ensuring a fallback to standard DMA(host memory) for the rest, if possible. Signed-off-by: Yonatan Maman Signed-off-by: Gal Shalom --- drivers/infiniband/hw/mlx5/odp.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/odp.c b/drivers/infiniband/hw/mlx5/odp.c index fbb2a5670c32..f7a1291ec7d1 100644 --- a/drivers/infiniband/hw/mlx5/odp.c +++ b/drivers/infiniband/hw/mlx5/odp.c @@ -169,6 +169,7 @@ static int populate_mtt(__be64 *pas, size_t start, size_t nentries, struct pci_p2pdma_map_state p2pdma_state = {}; struct ib_device *dev = odp->umem.ibdev; size_t i; + int ret = 0; if (flags & MLX5_IB_UPD_XLT_ZAP) return 0; @@ -184,8 +185,11 @@ static int populate_mtt(__be64 *pas, size_t start, size_t nentries, dma_addr = hmm_dma_map_pfn(dev->dma_device, &odp->map, start + i, &p2pdma_state); - if (ib_dma_mapping_error(dev, dma_addr)) - return -EFAULT; + if (ib_dma_mapping_error(dev, dma_addr)) { + odp->map.pfn_list[start + i] &= ~(HMM_PFN_ALLOW_P2P); + ret = -EFAULT; + continue; + } dma_addr |= MLX5_IB_MTT_READ; if ((pfn & HMM_PFN_WRITE) && !downgrade) @@ -194,7 +198,7 @@ static int populate_mtt(__be64 *pas, size_t start, size_t nentries, pas[i] = cpu_to_be64(dma_addr); odp->npages++; } - return 0; + return ret; } int mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, @@ -696,6 +700,10 @@ static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp, if (odp->umem.writable && !downgrade) access_mask |= HMM_PFN_WRITE; + /* + * try fault with HMM_PFN_ALLOW_P2P flag + */ + access_mask |= HMM_PFN_ALLOW_P2P; np = ib_umem_odp_map_dma_and_lock(odp, user_va, bcnt, access_mask, fault); if (np < 0) return np; @@ -705,6 +713,16 @@ static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp, * ib_umem_odp_map_dma_and_lock already checks this. */ ret = mlx5r_umr_update_xlt(mr, start_idx, np, page_shift, xlt_flags); + if (ret == -EFAULT) { + /* + * Indicate P2P Mapping Error, retry with no HMM_PFN_ALLOW_P2P + */ + access_mask &= ~HMM_PFN_ALLOW_P2P; + np = ib_umem_odp_map_dma_and_lock(odp, user_va, bcnt, access_mask, fault); + if (np < 0) + return np; + ret = mlx5r_umr_update_xlt(mr, start_idx, np, page_shift, xlt_flags); + } mutex_unlock(&odp->umem_mutex); if (ret < 0) {