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Wed, 4 Dec 2024 15:38:39 -0600 From: Lizhi Hou To: , , CC: Lizhi Hou , , , , , , , Xiaoming Ren Subject: [PATCH V1 3/7] accel/amdxdna: Add RyzenAI-npu6 support Date: Wed, 4 Dec 2024 13:37:25 -0800 Message-ID: <20241204213729.3113941-4-lizhi.hou@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204213729.3113941-1-lizhi.hou@amd.com> References: <20241204213729.3113941-1-lizhi.hou@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: lizhi.hou@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|PH7PR12MB7966:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e019406-c08f-4c5e-78ee-08dd14ac0565 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: bIlRSnojxcG/Fofx2MWsFpR9rcVazYsCDPDU5K9qM1iioX1YLK/ez3lFEI86b1MvAF4kY3JgbOo2qfwib3CGsddtrylc1nEEQffoPgKN4NUavQk7o46TqgQ+aYtQuo8WsQn+jw7joZdqI3g9gN4qTRAwn7tphfJ1YAC1lKXZEGePcuO6gerEUmmoONIMBXyypaBE9xLudVukOUyma7zKLSufWs+rml88CwfVlwSlJxwV5id8znDSFejqCYPJlDDMEUmayJ7ug8E418Dw4ozbGeDfnzwN0Gj9s+wRE2NEVyxlaYil4Ie+4P9UshXaqtXY0xETHnUQaG0x4VH3l1ZBFvGU2ftRfpbn1xmASrbWfcbvMVO9U5KWU/azvyi+D0pU1DIMhV8+IH+aUUQxTeOfOy1AAFKKZrZ877UeV1jLmoFQRdzOJ419yTeRWXAKN6n0B107feaGCi7FjlLy0EFjAOxicZdoxqynArjxhDKUhk6/H+OvI/NbHJyDKnYkFpNIYV1Roqtwy/PCUFNHNmJIiBo2NA7L2QLGTG+AiYND2C/aFllGnZhSGOxD97ZJvLEenl9AodS98rH7oHtShYV+IfYdJkTEwpqqx/xsSVyORbP1txOUFNdOMHOluLh2yjvYioj0E7OFIMci9V2eWvjO7aSNY9dRPL4322Lg0H3USrzXBDKbxWWZ8Cz+DIyfqSn9LVflQJWjC6jSQkrHau86KITsAC652liQzdfZJ02aYwrG+4+1vz3sBDH9PCtAYLHN0bOW1IXth9gjtubh2WaW0sEkwUa23SNC0ImtC72LEn+5+7tQJUtGNC2GgayE3cugm+kd9Mvydd+7SVNMBknqUdQspLCZUZl31EFzUB9VCo2H98Id8LzRN4/griMzDMZsr/nHEh2jmhlODBwhGZ53nwj0j+XsAXzp3u4Kem2sdjZ7RuJeXSR4ZC5gSmZjnG5w41bhXzHZushfeu1jI/hSM4hZ5+tPHyhiq6xQR7OPXE5ZvvdVJ3jFRg/dyy+VAp4x0g2GQfLOYfhdUBCJg3EvTk+HI0FcderiuedQW698/6eZx2TjgUXfHf9sabhCkrdUTUePzeGP//L94IsWv1XZ5Hq5RtuVyqvIvEEk1pV7yg3tYwgFKO8HWAS33uZKkMjxh2JZizTeSkXkoOyPG314rcdMrbdAb5sEYsphKJ5rZwJEY9SZRKB6wOWMq3EmzqWsCeqINFfg9O5xu0cmJ8FpLDaF8O222k5WuPMHXLX9gFIL3j2U/5L0KoIySf2zzl6CyhvkaXrLPnBwJf1XnAAQCthoL71poAdvhTuWkbsw1OuOazZtzWLV/HnyJhzGrxmUYl4WcvQaeFxA031P7mBfMMzMCc5THtK2tB129YVDkY+CpryVap5H4IPqnFAjd6YqN3ssTFrDq3Cs+mO/wYC2oMP8Xn4l0efdSkoDuBUsngzphYCx/GtGAZwKiNZtiwWb X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2024 21:38:41.3163 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e019406-c08f-4c5e-78ee-08dd14ac0565 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7966 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add NPU6 registers and other private configurations. Co-developed-by: Xiaoming Ren Signed-off-by: Xiaoming Ren Signed-off-by: Lizhi Hou --- drivers/accel/amdxdna/Makefile | 3 +- drivers/accel/amdxdna/npu6_regs.c | 121 ++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 drivers/accel/amdxdna/npu6_regs.c diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile index ed6f87910880..6baf181298de 100644 --- a/drivers/accel/amdxdna/Makefile +++ b/drivers/accel/amdxdna/Makefile @@ -17,5 +17,6 @@ amdxdna-y := \ npu1_regs.o \ npu2_regs.o \ npu4_regs.o \ - npu5_regs.o + npu5_regs.o \ + npu6_regs.o obj-$(CONFIG_DRM_ACCEL_AMDXDNA) = amdxdna.o diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c new file mode 100644 index 000000000000..d1168fc55533 --- /dev/null +++ b/drivers/accel/amdxdna/npu6_regs.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include + +#include "aie2_pci.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_pci_drv.h" + +/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ +#define MPNPU_PUB_SEC_INTR 0x3010060 +#define MPNPU_PUB_PWRMGMT_INTR 0x3010064 +#define MPNPU_PUB_SCRATCH0 0x301006C +#define MPNPU_PUB_SCRATCH1 0x3010070 +#define MPNPU_PUB_SCRATCH2 0x3010074 +#define MPNPU_PUB_SCRATCH3 0x3010078 +#define MPNPU_PUB_SCRATCH4 0x301007C +#define MPNPU_PUB_SCRATCH5 0x3010080 +#define MPNPU_PUB_SCRATCH6 0x3010084 +#define MPNPU_PUB_SCRATCH7 0x3010088 +#define MPNPU_PUB_SCRATCH8 0x301008C +#define MPNPU_PUB_SCRATCH9 0x3010090 +#define MPNPU_PUB_SCRATCH10 0x3010094 +#define MPNPU_PUB_SCRATCH11 0x3010098 +#define MPNPU_PUB_SCRATCH12 0x301009C +#define MPNPU_PUB_SCRATCH13 0x30100A0 +#define MPNPU_PUB_SCRATCH14 0x30100A4 +#define MPNPU_PUB_SCRATCH15 0x30100A8 +#define MP0_C2PMSG_73 0x3810A24 +#define MP0_C2PMSG_123 0x3810AEC + +#define MP1_C2PMSG_0 0x3B10900 +#define MP1_C2PMSG_60 0x3B109F0 +#define MP1_C2PMSG_61 0x3B109F4 + +#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 +#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 +#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 +#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 + +#define MMNPU_APERTURE0_BASE 0x3000000 +#define MMNPU_APERTURE1_BASE 0x3600000 +#define MMNPU_APERTURE3_BASE 0x3810000 +#define MMNPU_APERTURE4_BASE 0x3B10000 + +/* PCIe BAR Index for NPU6 */ +#define NPU6_REG_BAR_INDEX 0 +#define NPU6_MBOX_BAR_INDEX 0 +#define NPU6_PSP_BAR_INDEX 4 +#define NPU6_SMU_BAR_INDEX 5 +#define NPU6_SRAM_BAR_INDEX 2 +/* Associated BARs and Apertures */ +#define NPU6_REG_BAR_BASE MMNPU_APERTURE0_BASE +#define NPU6_MBOX_BAR_BASE MMNPU_APERTURE0_BASE +#define NPU6_PSP_BAR_BASE MMNPU_APERTURE3_BASE +#define NPU6_SMU_BAR_BASE MMNPU_APERTURE4_BASE +#define NPU6_SRAM_BAR_BASE MMNPU_APERTURE1_BASE + +#define NPU6_RT_CFG_TYPE_PDI_LOAD 5 +#define NPU6_RT_CFG_TYPE_DEBUG_BO 10 + +#define NPU6_RT_CFG_VAL_PDI_LOAD_MGMT 0 +#define NPU6_RT_CFG_VAL_PDI_LOAD_APP 1 + +#define NPU6_RT_CFG_VAL_DEBUG_BO_DEFAULT 0 +#define NPU6_RT_CFG_VAL_DEBUG_BO_LARGE 1 + +#define NPU6_MPNPUCLK_FREQ_MAX 1267 +#define NPU6_HCLK_FREQ_MAX 1800 + +const struct amdxdna_dev_priv npu6_dev_priv = { + .fw_path = "amdnpu/17f0_10/npu.sbin", + .protocol_major = 0x6, + .protocol_minor = 12, + .rt_config = {NPU6_RT_CFG_TYPE_PDI_LOAD, NPU6_RT_CFG_VAL_PDI_LOAD_APP}, + .col_align = COL_ALIGN_NATURE, + .mbox_dev_addr = NPU6_MBOX_BAR_BASE, + .mbox_size = 0, /* Use BAR size */ + .sram_dev_addr = NPU6_SRAM_BAR_BASE, + .sram_offs = { + DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), + DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), + }, + .psp_regs_off = { + DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123), + DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), + DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU6_REG, MPNPU_PUB_SCRATCH4), + DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU6_REG, MPNPU_PUB_SCRATCH9), + DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73), + DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123), + DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), + }, + .smu_regs_off = { + DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0), + DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU6_SMU, MP1_C2PMSG_60), + DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE), + DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61), + DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60), + }, +}; + +const struct amdxdna_dev_info dev_npu6_info = { + .reg_bar = NPU6_REG_BAR_INDEX, + .mbox_bar = NPU6_MBOX_BAR_INDEX, + .sram_bar = NPU6_SRAM_BAR_INDEX, + .psp_bar = NPU6_PSP_BAR_INDEX, + .smu_bar = NPU6_SMU_BAR_INDEX, + .first_col = 0, + .dev_mem_buf_shift = 15, /* 32 KiB aligned */ + .dev_mem_base = AIE2_DEVM_BASE, + .dev_mem_size = AIE2_DEVM_SIZE, + .vbnv = "RyzenAI-npu6", + .device_type = AMDXDNA_DEV_TYPE_KMQ, + .dev_priv = &npu6_dev_priv, + .ops = &aie2_ops, +};