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Fri, 06 Dec 2024 04:32:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B64WZ9A016351 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Dec 2024 04:32:35 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 20:32:34 -0800 From: Abhinav Kumar Date: Thu, 5 Dec 2024 20:31:50 -0800 Subject: [PATCH 19/45] drm/msm/dp: add support to program mst support in mainlink MIME-Version: 1.0 Message-ID: <20241205-dp_mst-v1-19-f8618d42a99a@quicinc.com> References: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> In-Reply-To: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , "Chandan Uddaraju" , Guenter Roeck , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Vara Reddy , Rob Clark , Tanmay Shah , , , , , , Jessica Zhang , Laurent Pinchart , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733459543; l=3002; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=9KLk+544O/3bV4KjALqN/xbTwPS+r5zHpCGcsu0weps=; b=GXx7yqK7P8j1e8dl9bwY/bmfgXEIEHIW6A46ala3ODDGFRlMiQgFzzp0JKm/71bbuvI+7OQxh 24e0chZGwZVANmdP5XYaXdBMUuZ1I2ur/bm+7M9D6P7Yp2FTq/Lsczp X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0w7tLV-GcCSzasnkDUOl7UvkPXIrH-1M X-Proofpoint-ORIG-GUID: 0w7tLV-GcCSzasnkDUOl7UvkPXIrH-1M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 phishscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=849 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060030 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support to program the MST enabled bit in the mainlink control when a mst session is active and disabled. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++++ 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 88d6262a972ef2d30c467ef5ff5c58ef3299ae7d..bdc66e5cab640c351708ba1a1bc3bca21784df6e 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -417,6 +417,23 @@ void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp_catal msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val); } +void msm_dp_catalog_mst_config(struct msm_dp_catalog *msm_dp_catalog, bool enable) +{ + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, + struct msm_dp_catalog_private, + msm_dp_catalog); + + u32 mainlink_ctrl; + + mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + if (enable) + mainlink_ctrl |= (0x04000100); + else + mainlink_ctrl &= ~(0x04000100); + + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catalog, bool enable) { diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index c91c52d40209b8bcb63db9c0256f6ef721dace8a..07284f484e2861aeae12b115cd05a94afed1c9cb 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -138,5 +138,6 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *catalog, u32 safe_to_ /* DP MST APIs */ void msm_dp_catalog_trigger_act(struct msm_dp_catalog *dp_catalog); bool msm_dp_catalog_read_act_complete_sts(struct msm_dp_catalog *dp_catalog); +void msm_dp_catalog_mst_config(struct msm_dp_catalog *dp_catalog, bool enable); #endif /* _DP_CATALOG_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 2bfe2aac3c02b02b12713dbd98e79ed4a75b85d0..3839f1e8e1aeb2a14a7f59c546693141a0df6323 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -186,6 +186,9 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog); msm_dp_catalog_setup_peripheral_flush(ctrl->catalog); + if (ctrl->mst_active) + msm_dp_catalog_mst_config(ctrl->catalog, true); + msm_dp_ctrl_config_ctrl(ctrl, msm_dp_panel); tb = msm_dp_link_get_test_bits_depth(ctrl->link, @@ -2132,6 +2135,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) phy = ctrl->phy; msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_catalog_mst_config(ctrl->catalog, false); ctrl->mst_active = false;