From patchwork Fri Dec 6 04:31:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13896459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1D51E77171 for ; Fri, 6 Dec 2024 04:33:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3937A10EFF3; Fri, 6 Dec 2024 04:33:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.b="Gc2DDBtt"; dkim-atps=neutral Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BF2710E609; Fri, 6 Dec 2024 04:33:11 +0000 (UTC) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B63jgdB006170; Fri, 6 Dec 2024 04:32:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hsYgAvy9mi/GR3uP7j4adY4IuHyTjTCDEZm2zViwvFQ=; b=Gc2DDBttRw/2IgJM l8vWiGr+Gt2SpWzMBIWkbLbnnCvSzEYEs7DtW0Z0znbBWwCZEh8JDGStOqUO9Xnq 0y5+eG/HV9w6wFDUCrgdpfPVN8Uyk6QAyzyqdTa92a2kaY5l0BmwH2XCSXyKeZIR i8BPSuqpXN8tf1VKfvs5LmELQdNCmB/a84O4mvUvWvxAMqBNamvfFlHDv8bopPVK kSgDb+pdPwRKZuSDfNZlLjkUEsWQSSNcZOa3LN4riSTu1gp/KZVT+F7gD+UiOrVV KxWdCwwXs8KSpS5szVHW6yQJ2qILzMtHBqyszZipr6SNkVDdVFW56rUqlC0H/Dap AglCrw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43bsn6r38f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Dec 2024 04:32:41 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B64WeWe022144 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Dec 2024 04:32:40 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 20:32:39 -0800 From: Abhinav Kumar Date: Thu, 5 Dec 2024 20:31:59 -0800 Subject: [PATCH 28/45] drm/msm/dp: add an API to initialize MST on sink side MIME-Version: 1.0 Message-ID: <20241205-dp_mst-v1-28-f8618d42a99a@quicinc.com> References: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> In-Reply-To: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , "Chandan Uddaraju" , Guenter Roeck , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Vara Reddy , Rob Clark , Tanmay Shah , , , , , , Jessica Zhang , Laurent Pinchart , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733459543; l=2208; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=svwpt0HBxsCFg7RickHTD3kd47ILnPbAStYvVUUY4Ls=; b=SeooClUcp4ViuyCxSxzx/EqkfyzdIcjyx2G0bqX7wotdbRwwLZLbvsQLSypz6Wd7CRIvTm6/O 8Q16sR6Q5v6BoPvZDEVGB6B4J/eBeW5pwolsaFcRp/hyIkbGaMBmFc+ X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Qs1vGdoz3UkPcy26cWZi72MF8qi1WL3W X-Proofpoint-ORIG-GUID: Qs1vGdoz3UkPcy26cWZi72MF8qi1WL3W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060030 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" If the DP controller is capable of supporting multiple streams then initialize the DP sink in MST mode by programming the DP_MSTM_CTRL DPCD register to enable MST mode. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/dp/dp_display.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index e69cdfbbe10484e47475ef189849f8ff6628bd7a..033d238e956263c1212fce45aab01316ef341edb 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -380,6 +380,35 @@ static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *d return 0; } +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) +{ + const unsigned long clear_mstm_ctrl_timeout_us = 100000; + u8 old_mstm_ctrl; + struct msm_dp *msm_dp = &dp->msm_dp_display; + int ret; + + /* clear sink mst state */ + drm_dp_dpcd_readb(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); + drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, 0); + + /* add extra delay if MST state is not cleared */ + if (old_mstm_ctrl) { + drm_dbg_dp(dp->drm_dev, "MSTM_CTRL is not cleared, wait %luus\n", + clear_mstm_ctrl_timeout_us); + usleep_range(clear_mstm_ctrl_timeout_us, + clear_mstm_ctrl_timeout_us + 1000); + } + + ret = drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink mst enablement failed\n"); + return; + } + + msm_dp->mst_active = true; +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) { struct drm_connector *connector = dp->msm_dp_display.connector; @@ -414,6 +443,9 @@ static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); + if (dp->max_stream > DEFAULT_STREAM_COUNT && msm_dp_panel_read_mst_cap(dp->panel)) + msm_dp_display_mst_init(dp); + msm_dp_link_reset_phy_params_vx_px(dp->link); rc = msm_dp_ctrl_on_link(dp->ctrl, dp_display->mst_active); if (rc) {