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Fri, 6 Dec 2024 16:00:16 -0600 Received: from xsjlizhih51.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 6 Dec 2024 16:00:15 -0600 From: Lizhi Hou To: , , CC: Lizhi Hou , , , , , , , Xiaoming Ren Subject: [PATCH V2 3/8] accel/amdxdna: Add RyzenAI-npu6 support Date: Fri, 6 Dec 2024 13:59:56 -0800 Message-ID: <20241206220001.164049-4-lizhi.hou@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241206220001.164049-1-lizhi.hou@amd.com> References: <20241206220001.164049-1-lizhi.hou@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C8:EE_|IA1PR12MB6649:EE_ X-MS-Office365-Filtering-Correlation-Id: 051a830e-9000-494c-3199-08dd16415eb5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: lUO1nUGLdGwkFm3VIT6Rqb7uOLC7lr8sVwKjNuo/m1I/QHH6sG2cf2puPnvC5Zs2NEDJgYTDnNCDSzUYlz8cyKqWrKJCh1ZHmKtq4Fn0kSTb6aHGDSUWBHOY520aWDOv9l+F2iXHRXEw9SjOR+XnNNYkWVWL4Vu94pu2yFRVZ9qbMSnX53FtOdsb8ffZonyuJCHGXZcGM+5etnQ1OjGSmVFH+RNNMf49245Ck7KAhn2PE010pR9tPvlUMrMLnl4fhbM8DTNhBEzi0mF7wJM9POJYZpLqUL3HFhO7CQGL7m/AcyBP4LCN20lD6IgthgNh12BKLHtcvPP3+x7bcT2nhGlU20v1rOgN8e2KUlsJ8AhKp6dijZRYj0S7cqvtEBJm89ky5cCXZhbcxY12+zAnEwazZShz0iqRVxTs6+QpfQD+GfrsFBkrfhQO7pDBvHpU5afuz/BkoY1rvbL2jS2BORG9yN9doDdRvI7kY7m9JEaEsybf9c0bSDmWMOfP+dl4gT6AbyeavspSMxoLYzLeEaAgSPkwYu1x12E9fNc2jnzWdbf3uy/jRHvE9LgsTZ9SYZO8fjb8uYIhkMgUSOuO0jjHqinmyLIkX5vB6DVMLX5A21tLzks8sHmwjsUkUkp+iD+AZyxUpEEftc1PQ/HmD+JHEdih4hs7b7DdLOrIYCSR52gswjrIsKnUJHZKVtLVeW/TT/WE1TyaLO5902IGwBXDHd84kMX7qT3OmitF//le8avgjyYIzKZZudr/kLRjftX9L1BaRl+ZPaRT40mmxikAEHv/FYnSmKKha/DrgS4PSk+1qHBqaOkpcOsmv8X/y62Ra44Z1kWbPeAYP7ZDMlWVhbN1IVj53nilOEv7OyFRKM3e/xGakk8KuJNMZv1RcDSH5jAnY5dhewNawAE7cU4gpT8B0DpfdjoAQ1fSd25kPz0rgjev226yyiwarEd+H72IAvrFr//o3MUheytYLZorykBZLXSkGd0K6uYGEj3URHAgtcZhxe++mVJf3jBAQBK5Nk4xPg5FXjqj5aB0kbLHGpBWkKK1IhciOQimdwO7z6769QlCLR/UOSb6S7QfluMjXBmdJa17GOjKOU8tfkBwa4QsenDZ1TMYgQgE3wqXtos31y/woN5ZFcudXB3+DfUvj/2jB55Ge451F9gHkmOuETLNV55CFK31EmZU1xKD6tnKfH1af5Lmh9YimOqAViQ+WSIkTaV64r0RK8mcgzVaSdPDxc7DkIHEoOkmfTMy4GIFM0NGtasYo/+EVUX8O+u8bEFgfR87ee+1xDCtfNPi9jgQUz6pKNt8yLj6wo12pC1EhE4MCk2F+DpV2vCOh3UctqC1PwzzQrkA3yHewdI2sCeqpedCBJf+UOB2PYu+UFsCaPfoYnN5Oye4FtFXWr+mEZF4LBaotSth4C2fBq2p+cKlJK+SzHKoBqKgFF3gnkos+XaF0YeNvtS0pwwV X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2024 22:00:17.3003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 051a830e-9000-494c-3199-08dd16415eb5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6649 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add NPU6 registers and other private configurations. Co-developed-by: Xiaoming Ren Signed-off-by: Xiaoming Ren Signed-off-by: Lizhi Hou Reviewed-by: Mario Limonciello --- drivers/accel/amdxdna/Makefile | 3 +- drivers/accel/amdxdna/npu6_regs.c | 121 ++++++++++++++++++++++++++++++ 2 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 drivers/accel/amdxdna/npu6_regs.c diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile index ed6f87910880..6baf181298de 100644 --- a/drivers/accel/amdxdna/Makefile +++ b/drivers/accel/amdxdna/Makefile @@ -17,5 +17,6 @@ amdxdna-y := \ npu1_regs.o \ npu2_regs.o \ npu4_regs.o \ - npu5_regs.o + npu5_regs.o \ + npu6_regs.o obj-$(CONFIG_DRM_ACCEL_AMDXDNA) = amdxdna.o diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c new file mode 100644 index 000000000000..d1168fc55533 --- /dev/null +++ b/drivers/accel/amdxdna/npu6_regs.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include + +#include "aie2_pci.h" +#include "amdxdna_mailbox.h" +#include "amdxdna_pci_drv.h" + +/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ +#define MPNPU_PUB_SEC_INTR 0x3010060 +#define MPNPU_PUB_PWRMGMT_INTR 0x3010064 +#define MPNPU_PUB_SCRATCH0 0x301006C +#define MPNPU_PUB_SCRATCH1 0x3010070 +#define MPNPU_PUB_SCRATCH2 0x3010074 +#define MPNPU_PUB_SCRATCH3 0x3010078 +#define MPNPU_PUB_SCRATCH4 0x301007C +#define MPNPU_PUB_SCRATCH5 0x3010080 +#define MPNPU_PUB_SCRATCH6 0x3010084 +#define MPNPU_PUB_SCRATCH7 0x3010088 +#define MPNPU_PUB_SCRATCH8 0x301008C +#define MPNPU_PUB_SCRATCH9 0x3010090 +#define MPNPU_PUB_SCRATCH10 0x3010094 +#define MPNPU_PUB_SCRATCH11 0x3010098 +#define MPNPU_PUB_SCRATCH12 0x301009C +#define MPNPU_PUB_SCRATCH13 0x30100A0 +#define MPNPU_PUB_SCRATCH14 0x30100A4 +#define MPNPU_PUB_SCRATCH15 0x30100A8 +#define MP0_C2PMSG_73 0x3810A24 +#define MP0_C2PMSG_123 0x3810AEC + +#define MP1_C2PMSG_0 0x3B10900 +#define MP1_C2PMSG_60 0x3B109F0 +#define MP1_C2PMSG_61 0x3B109F4 + +#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 +#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 +#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 +#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 + +#define MMNPU_APERTURE0_BASE 0x3000000 +#define MMNPU_APERTURE1_BASE 0x3600000 +#define MMNPU_APERTURE3_BASE 0x3810000 +#define MMNPU_APERTURE4_BASE 0x3B10000 + +/* PCIe BAR Index for NPU6 */ +#define NPU6_REG_BAR_INDEX 0 +#define NPU6_MBOX_BAR_INDEX 0 +#define NPU6_PSP_BAR_INDEX 4 +#define NPU6_SMU_BAR_INDEX 5 +#define NPU6_SRAM_BAR_INDEX 2 +/* Associated BARs and Apertures */ +#define NPU6_REG_BAR_BASE MMNPU_APERTURE0_BASE +#define NPU6_MBOX_BAR_BASE MMNPU_APERTURE0_BASE +#define NPU6_PSP_BAR_BASE MMNPU_APERTURE3_BASE +#define NPU6_SMU_BAR_BASE MMNPU_APERTURE4_BASE +#define NPU6_SRAM_BAR_BASE MMNPU_APERTURE1_BASE + +#define NPU6_RT_CFG_TYPE_PDI_LOAD 5 +#define NPU6_RT_CFG_TYPE_DEBUG_BO 10 + +#define NPU6_RT_CFG_VAL_PDI_LOAD_MGMT 0 +#define NPU6_RT_CFG_VAL_PDI_LOAD_APP 1 + +#define NPU6_RT_CFG_VAL_DEBUG_BO_DEFAULT 0 +#define NPU6_RT_CFG_VAL_DEBUG_BO_LARGE 1 + +#define NPU6_MPNPUCLK_FREQ_MAX 1267 +#define NPU6_HCLK_FREQ_MAX 1800 + +const struct amdxdna_dev_priv npu6_dev_priv = { + .fw_path = "amdnpu/17f0_10/npu.sbin", + .protocol_major = 0x6, + .protocol_minor = 12, + .rt_config = {NPU6_RT_CFG_TYPE_PDI_LOAD, NPU6_RT_CFG_VAL_PDI_LOAD_APP}, + .col_align = COL_ALIGN_NATURE, + .mbox_dev_addr = NPU6_MBOX_BAR_BASE, + .mbox_size = 0, /* Use BAR size */ + .sram_dev_addr = NPU6_SRAM_BAR_BASE, + .sram_offs = { + DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), + DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), + }, + .psp_regs_off = { + DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123), + DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), + DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU6_REG, MPNPU_PUB_SCRATCH4), + DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU6_REG, MPNPU_PUB_SCRATCH9), + DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73), + DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123), + DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), + }, + .smu_regs_off = { + DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0), + DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU6_SMU, MP1_C2PMSG_60), + DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE), + DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61), + DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60), + }, +}; + +const struct amdxdna_dev_info dev_npu6_info = { + .reg_bar = NPU6_REG_BAR_INDEX, + .mbox_bar = NPU6_MBOX_BAR_INDEX, + .sram_bar = NPU6_SRAM_BAR_INDEX, + .psp_bar = NPU6_PSP_BAR_INDEX, + .smu_bar = NPU6_SMU_BAR_INDEX, + .first_col = 0, + .dev_mem_buf_shift = 15, /* 32 KiB aligned */ + .dev_mem_base = AIE2_DEVM_BASE, + .dev_mem_size = AIE2_DEVM_SIZE, + .vbnv = "RyzenAI-npu6", + .device_type = AMDXDNA_DEV_TYPE_KMQ, + .dev_priv = &npu6_dev_priv, + .ops = &aie2_ops, +};