From patchwork Sat Dec 7 21:32:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13898408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B83BE7717F for ; Sat, 7 Dec 2024 21:33:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A363910E347; Sat, 7 Dec 2024 21:32:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="h1J9Wef4"; dkim-atps=neutral Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id E12AA10E27C for ; Sat, 7 Dec 2024 21:32:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1733607173; bh=DuquKXFrrFxNB+/27gdv/HCQ8M7uGVTRTKsJMPlOXKI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=h1J9Wef4KeKI4JXzeuvLmnYTV77d0z+0e53Y7dExy+ffZBBtoZ+ZWccb8AhIo4Tii /J197bavNgzrDkOI20AXfASZnQlasP92u3PtCqnRcl7Hyps77Xvqh2vlw1v0TuzQ5X ppU5eSnwsdlCgTVFPGi+q+obBOIiEikQQigUblX3soAZ4GEB7ektNn+z2atE1723rr H93k3dglMbnFiFcYeVb2Kw7KusCPdyOweoirhTqiyhiWsriyil2ScA/r5XbxV7D7MV 8UPMCVrUZ6eTwEfvBcdkYpVsNtdxPIyJSeX6X4e5mk5AXLiZk0cpIb9aGfH5LcUNZs M5uXnb5ZqnfCQ== Received: from localhost (unknown [188.27.48.199]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2C53117E3803; Sat, 7 Dec 2024 22:32:53 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 07 Dec 2024 23:32:25 +0200 Subject: [PATCH 2/4] arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588 MIME-Version: 1.0 Message-Id: <20241207-rk3588-hdmi1-v1-2-ca3a99b46a40@collabora.com> References: <20241207-rk3588-hdmi1-v1-0-ca3a99b46a40@collabora.com> In-Reply-To: <20241207-rk3588-hdmi1-v1-0-ca3a99b46a40@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation to enable the second HDMI output port found on RK3588 SoC, add the related PHY node. This requires a GRF, hence add the dependent node as well. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 0ce0934ec6b793af45585f67d5312434d80357de..68fa9806164776cef8732bb776e958003779ba28 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -67,6 +67,11 @@ u2phy1_otg: otg-port { }; }; + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -395,6 +400,22 @@ sata-port@0 { }; }; + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + status = "disabled"; + }; + usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>;